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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | import sigrokdecode as srd | |
23 | ||
24 | ''' | |
25 | OUTPUT_PYTHON format: | |
26 | ||
27 | Packet: | |
28 | [<ptype>, <data1>, <data2>] | |
29 | ||
30 | <ptype>: | |
31 | - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data. | |
32 | The data is _usually_ 8 bits (but can also be fewer or more bits). | |
33 | Both data items are Python numbers (not strings), or None if the respective | |
34 | channel was not supplied. | |
35 | - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data | |
36 | item, and for each of those also their respective start-/endsample numbers. | |
37 | - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value. | |
38 | Both data items are Python numbers (0/1), not strings. | |
39 | ||
40 | Examples: | |
41 | ['CS-CHANGE', 1, 0] | |
42 | ['DATA', 0xff, 0x3a] | |
43 | ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], | |
44 | [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], | |
45 | [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88], | |
46 | [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]] | |
47 | ['DATA', 0x65, 0x00] | |
48 | ['DATA', 0xa8, None] | |
49 | ['DATA', None, 0x55] | |
50 | ['CS-CHANGE', 0, 1] | |
51 | ''' | |
52 | ||
53 | # Key: (CPOL, CPHA). Value: SPI mode. | |
54 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. | |
55 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
56 | spi_mode = { | |
57 | (0, 0): 0, # Mode 0 | |
58 | (0, 1): 1, # Mode 1 | |
59 | (1, 0): 2, # Mode 2 | |
60 | (1, 1): 3, # Mode 3 | |
61 | } | |
62 | ||
63 | class SamplerateError(Exception): | |
64 | pass | |
65 | ||
66 | class MissingDataError(Exception): | |
67 | pass | |
68 | ||
69 | class Decoder(srd.Decoder): | |
70 | api_version = 2 | |
71 | id = 'spi' | |
72 | name = 'SPI' | |
73 | longname = 'Serial Peripheral Interface' | |
74 | desc = 'Full-duplex, synchronous, serial bus.' | |
75 | license = 'gplv2+' | |
76 | inputs = ['logic'] | |
77 | outputs = ['spi'] | |
78 | channels = ( | |
79 | {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, | |
80 | ) | |
81 | optional_channels = ( | |
82 | {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, | |
83 | {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, | |
84 | {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, | |
85 | ) | |
86 | options = ( | |
87 | {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low', | |
88 | 'values': ('active-low', 'active-high')}, | |
89 | {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0, | |
90 | 'values': (0, 1)}, | |
91 | {'id': 'cpha', 'desc': 'Clock phase', 'default': 0, | |
92 | 'values': (0, 1)}, | |
93 | {'id': 'bitorder', 'desc': 'Bit order', | |
94 | 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')}, | |
95 | {'id': 'wordsize', 'desc': 'Word size', 'default': 8}, | |
96 | ) | |
97 | annotations = ( | |
98 | ('miso-data', 'MISO data'), | |
99 | ('mosi-data', 'MOSI data'), | |
100 | ('miso-bits', 'MISO bits'), | |
101 | ('mosi-bits', 'MOSI bits'), | |
102 | ('warnings', 'Human-readable warnings'), | |
103 | ) | |
104 | annotation_rows = ( | |
105 | ('miso-data', 'MISO data', (0,)), | |
106 | ('miso-bits', 'MISO bits', (2,)), | |
107 | ('mosi-data', 'MOSI data', (1,)), | |
108 | ('mosi-bits', 'MOSI bits', (3,)), | |
109 | ('other', 'Other', (4,)), | |
110 | ) | |
111 | ||
112 | def __init__(self): | |
113 | self.samplerate = None | |
114 | self.oldclk = 1 | |
115 | self.bitcount = 0 | |
116 | self.misodata = self.mosidata = 0 | |
117 | self.misobits = [] | |
118 | self.mosibits = [] | |
119 | self.startsample = -1 | |
120 | self.samplenum = -1 | |
121 | self.cs_was_deasserted = False | |
122 | self.oldcs = -1 | |
123 | self.oldpins = None | |
124 | self.have_cs = self.have_miso = self.have_mosi = None | |
125 | ||
126 | def metadata(self, key, value): | |
127 | if key == srd.SRD_CONF_SAMPLERATE: | |
128 | self.samplerate = value | |
129 | ||
130 | def start(self): | |
131 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
132 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
133 | self.out_bitrate = self.register(srd.OUTPUT_META, | |
134 | meta=(int, 'Bitrate', 'Bitrate during transfers')) | |
135 | ||
136 | def putw(self, data): | |
137 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
138 | ||
139 | def putdata(self): | |
140 | # Pass MISO and MOSI bits and then data to the next PD up the stack. | |
141 | so = self.misodata if self.have_miso else None | |
142 | si = self.mosidata if self.have_mosi else None | |
143 | so_bits = self.misobits if self.have_miso else None | |
144 | si_bits = self.mosibits if self.have_mosi else None | |
145 | ||
146 | if self.have_miso: | |
147 | ss, es = self.misobits[-1][1], self.misobits[0][2] | |
148 | if self.have_mosi: | |
149 | ss, es = self.mosibits[-1][1], self.mosibits[0][2] | |
150 | ||
151 | self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits]) | |
152 | self.put(ss, es, self.out_python, ['DATA', si, so]) | |
153 | ||
154 | # Bit annotations. | |
155 | if self.have_miso: | |
156 | for bit in self.misobits: | |
157 | self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]]) | |
158 | if self.have_mosi: | |
159 | for bit in self.mosibits: | |
160 | self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]]) | |
161 | ||
162 | # Dataword annotations. | |
163 | if self.have_miso: | |
164 | self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]]) | |
165 | if self.have_mosi: | |
166 | self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]]) | |
167 | ||
168 | def reset_decoder_state(self): | |
169 | self.misodata = 0 if self.have_miso else None | |
170 | self.mosidata = 0 if self.have_mosi else None | |
171 | self.misobits = [] if self.have_miso else None | |
172 | self.mosibits = [] if self.have_mosi else None | |
173 | self.bitcount = 0 | |
174 | ||
175 | def handle_bit(self, miso, mosi, clk, cs): | |
176 | # If this is the first bit of a dataword, save its sample number. | |
177 | if self.bitcount == 0: | |
178 | self.startsample = self.samplenum | |
179 | self.cs_was_deasserted = False | |
180 | if self.have_cs: | |
181 | active_low = (self.options['cs_polarity'] == 'active-low') | |
182 | self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0) | |
183 | ||
184 | ws = self.options['wordsize'] | |
185 | ||
186 | # Receive MISO bit into our shift register. | |
187 | if self.have_miso: | |
188 | if self.options['bitorder'] == 'msb-first': | |
189 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
190 | else: | |
191 | self.misodata |= miso << self.bitcount | |
192 | ||
193 | # Receive MOSI bit into our shift register. | |
194 | if self.have_mosi: | |
195 | if self.options['bitorder'] == 'msb-first': | |
196 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
197 | else: | |
198 | self.mosidata |= mosi << self.bitcount | |
199 | ||
200 | # Guesstimate the endsample for this bit (can be overridden below). | |
201 | es = self.samplenum | |
202 | if self.bitcount > 0: | |
203 | if self.have_miso: | |
204 | es += self.samplenum - self.misobits[0][1] | |
205 | elif self.have_mosi: | |
206 | es += self.samplenum - self.mosibits[0][1] | |
207 | ||
208 | if self.have_miso: | |
209 | self.misobits.insert(0, [miso, self.samplenum, es]) | |
210 | if self.have_mosi: | |
211 | self.mosibits.insert(0, [mosi, self.samplenum, es]) | |
212 | ||
213 | if self.bitcount > 0 and self.have_miso: | |
214 | self.misobits[1][2] = self.samplenum | |
215 | if self.bitcount > 0 and self.have_mosi: | |
216 | self.mosibits[1][2] = self.samplenum | |
217 | ||
218 | self.bitcount += 1 | |
219 | ||
220 | # Continue to receive if not enough bits were received, yet. | |
221 | if self.bitcount != ws: | |
222 | return | |
223 | ||
224 | self.putdata() | |
225 | ||
226 | # Meta bitrate. | |
227 | elapsed = 1 / float(self.samplerate) | |
228 | elapsed *= (self.samplenum - self.startsample + 1) | |
229 | bitrate = int(1 / elapsed * self.options['wordsize']) | |
230 | self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) | |
231 | ||
232 | if self.have_cs and self.cs_was_deasserted: | |
233 | self.putw([4, ['CS# was deasserted during this data word!']]) | |
234 | ||
235 | self.reset_decoder_state() | |
236 | ||
237 | def find_clk_edge(self, miso, mosi, clk, cs): | |
238 | if self.have_cs and self.oldcs != cs: | |
239 | # Send all CS# pin value changes. | |
240 | self.put(self.samplenum, self.samplenum, self.out_python, | |
241 | ['CS-CHANGE', self.oldcs, cs]) | |
242 | self.oldcs = cs | |
243 | # Reset decoder state when CS# changes (and the CS# pin is used). | |
244 | self.reset_decoder_state() | |
245 | ||
246 | # Ignore sample if the clock pin hasn't changed. | |
247 | if clk == self.oldclk: | |
248 | return | |
249 | ||
250 | self.oldclk = clk | |
251 | ||
252 | # Sample data on rising/falling clock edge (depends on mode). | |
253 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
254 | if mode == 0 and clk == 0: # Sample on rising clock edge | |
255 | return | |
256 | elif mode == 1 and clk == 1: # Sample on falling clock edge | |
257 | return | |
258 | elif mode == 2 and clk == 1: # Sample on falling clock edge | |
259 | return | |
260 | elif mode == 3 and clk == 0: # Sample on rising clock edge | |
261 | return | |
262 | ||
263 | # Found the correct clock edge, now get the SPI bit(s). | |
264 | self.handle_bit(miso, mosi, clk, cs) | |
265 | ||
266 | def decode(self, ss, es, data): | |
267 | if not self.samplerate: | |
268 | raise SamplerateError('Cannot decode without samplerate.') | |
269 | # Either MISO or MOSI can be omitted (but not both). CS# is optional. | |
270 | for (self.samplenum, pins) in data: | |
271 | ||
272 | # Ignore identical samples early on (for performance reasons). | |
273 | if self.oldpins == pins: | |
274 | continue | |
275 | self.oldpins, (clk, miso, mosi, cs) = pins, pins | |
276 | self.have_miso = (miso in (0, 1)) | |
277 | self.have_mosi = (mosi in (0, 1)) | |
278 | self.have_cs = (cs in (0, 1)) | |
279 | ||
280 | # Either MISO or MOSI (but not both) can be omitted. | |
281 | if not (self.have_miso or self.have_mosi): | |
282 | raise MissingDataError('Either MISO or MOSI (or both) pins required.') | |
283 | ||
284 | self.find_clk_edge(miso, mosi, clk, cs) |