]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode | |
22 | ||
23 | class Decoder(sigrokdecode.Decoder): | |
24 | id = 'spi' | |
25 | name = 'SPI' | |
26 | desc = '...desc...' | |
27 | longname = 'Serial Peripheral Interface (SPI) bus' | |
28 | longdesc = '...longdesc...' | |
29 | author = 'Gareth McMullin' | |
30 | email = 'gareth@blacksphere.co.nz' | |
31 | license = 'gplv2+' | |
32 | inputs = ['logic'] | |
33 | outputs = ['spi'] | |
34 | probes = [ | |
35 | {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'}, | |
36 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, | |
37 | ] | |
38 | options = {} | |
39 | ||
40 | def __init__(self): | |
41 | self.oldsck = 1 | |
42 | self.rxcount = 0 | |
43 | self.rxdata = 0 | |
44 | self.bytesreceived = 0 | |
45 | self.output_protocol = None | |
46 | self.output_annotation = None | |
47 | ||
48 | def start(self, metadata): | |
49 | # self.output_protocol = self.output_new(2) | |
50 | self.output_annotation = self.output_new(1) | |
51 | ||
52 | def report(self): | |
53 | return 'SPI: %d bytes received' % self.bytesreceived | |
54 | ||
55 | def decode(self, timeoffset, duration, data): | |
56 | # HACK! At the moment the number of probes is not handled correctly. | |
57 | # E.g. if an input file (-i foo.sr) has more than two probes enabled. | |
58 | for (samplenum, (sdata, sck, x, y, z, a)) in data: | |
59 | ||
60 | # Sample SDATA on rising SCK | |
61 | if sck == self.oldsck: | |
62 | continue | |
63 | self.oldsck = sck | |
64 | if not sck: | |
65 | continue | |
66 | ||
67 | # If this is first bit, save timestamp | |
68 | if self.rxcount == 0: | |
69 | self.time = timeoffset # FIXME | |
70 | # Receive bit into our shift register | |
71 | if sdata: | |
72 | self.rxdata |= 1 << (7 - self.rxcount) | |
73 | self.rxcount += 1 | |
74 | # Continue to receive if not a byte yet | |
75 | if self.rxcount != 8: | |
76 | continue | |
77 | # Received a byte, pass up to sigrok | |
78 | outdata = {'time':self.time, | |
79 | 'duration':timeoffset + duration - self.time, | |
80 | 'data':self.rxdata, | |
81 | 'display':('%02X' % self.rxdata), | |
82 | 'type':'spi', | |
83 | } | |
84 | # self.put(0, 0, self.output_protocol, out_proto) | |
85 | self.put(0, 0, self.output_annotation, outdata) | |
86 | # Reset decoder state | |
87 | self.rxdata = 0 | |
88 | self.rxcount = 0 | |
89 | # Keep stats for summary | |
90 | self.bytesreceived += 1 | |
91 |