[libsigrokdecode.git] / decoders / spi.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# Chip-select options
ACTIVE_LOW = 0
ACTIVE_HIGH = 1

# Clock polarity options
CPOL_0 = 0 # Clock is low when inactive
CPOL_1 = 1 # Clock is high when inactive

# Clock phase options
CPHA_0 = 0 # Data is valid on the leading clock edge
CPHA_1 = 1 # Data is valid on the trailing clock edge

# Bit order options
MSB_FIRST = 0
LSB_FIRST = 1

spi_mode = {
    (0, 0): 0, # Mode 0
    (0, 1): 1, # Mode 1
    (1, 0): 2, # Mode 2
    (1, 1): 3, # Mode 3
}

# Annotation formats
ANN_HEX = 0

class Decoder(srd.Decoder):
    id = 'spi'
    name = 'SPI'
    longname = 'Serial Peripheral Interface (SPI) bus'
    desc = '...desc...'
    longdesc = '...longdesc...'
    author = 'Gareth McMullin'
    email = 'gareth@blacksphere.co.nz'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['spi']
    probes = [
        {'id': 'mosi', 'name': 'MOSI',
         'desc': 'SPI MOSI line (Master out, slave in)'},
        {'id': 'miso', 'name': 'MISO',
         'desc': 'SPI MISO line (Master in, slave out)'},
        {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
    ]
    options = {
        'cs_polarity': ['CS# polarity', ACTIVE_LOW],
        'cpol': ['Clock polarity', CPOL_0],
        'cpha': ['Clock phase', CPHA_0],
        'bitorder': ['Bit order within the SPI data', MSB_FIRST],
        'wordsize': ['Word size of SPI data', 8], # 1-64?
    }
    annotations = [
        ['Hex', 'SPI data bytes in hex format'],
    ]

    def __init__(self):
        self.oldsck = 1
        self.bitcount = 0
        self.mosidata = 0
        self.misodata = 0
        self.bytesreceived = 0
        self.samplenum = -1
        self.cs_was_deasserted_during_data_word = 0

        # Set protocol decoder option defaults.
        self.cs_polarity = Decoder.options['cs_polarity'][1]
        self.cpol = Decoder.options['cpol'][1]
        self.cpha = Decoder.options['cpha'][1]
        self.bitorder = Decoder.options['bitorder'][1]
        self.wordsize = Decoder.options['wordsize'][1]

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')

    def report(self):
        return 'SPI: %d bytes received' % self.bytesreceived

    def decode(self, ss, es, data):
        # HACK! At the moment the number of probes is not handled correctly.
        # E.g. if an input file (-i foo.sr) has more than two probes enabled.
        # for (samplenum, (mosi, sck, x, y, z, a)) in data:
        # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
        for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:

            self.samplenum += 1 # FIXME

            # Ignore sample if the clock pin hasn't changed.
            if sck == self.oldsck:
                continue

            self.oldsck = sck

            # Sample data on rising/falling clock edge (depends on mode).
            mode = spi_mode[self.cpol, self.cpha]
            if mode == 0 and sck == 0:   # Sample on rising clock edge
                    continue
            elif mode == 1 and sck == 1: # Sample on falling clock edge
                    continue
            elif mode == 2 and sck == 1: # Sample on falling clock edge
                    continue
            elif mode == 3 and sck == 0: # Sample on rising clock edge
                    continue

            # If this is the first bit, save its sample number.
            if self.bitcount == 0:
                self.start_sample = samplenum
                deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c
                if deasserted:
                    self.cs_was_deasserted_during_data_word = 1

            # Receive MOSI bit into our shift register.
            if self.bitorder == MSB_FIRST:
                self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount)
            else:
                self.mosidata |= mosi << self.bitcount

            # Receive MISO bit into our shift register.
            if self.bitorder == MSB_FIRST:
                self.misodata |= miso << (self.wordsize - 1 - self.bitcount)
            else:
                self.misodata |= miso << self.bitcount

            self.bitcount += 1

            # Continue to receive if not a byte yet.
            if self.bitcount != self.wordsize:
                continue

            self.put(self.start_sample, self.samplenum, self.out_proto,
                     ['data', self.mosidata, self.misodata])
            self.put(self.start_sample, self.samplenum, self.out_ann,
                     [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                     self.misodata)]])

            if self.cs_was_deasserted_during_data_word:
                self.put(self.start_sample, self.samplenum, self.out_ann,
                         [ANN_HEX, ['WARNING: CS# was deasserted during this '
                         'SPI data byte!']])

            # Reset decoder state.
            self.mosidata = 0
            self.misodata = 0
            self.bitcount = 0

            # Keep stats for summary.
            self.bytesreceived += 1
Commit	Line	Data
	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	import sigrokdecode as srd
	23
	24	# Chip-select options
	25	ACTIVE_LOW = 0
	26	ACTIVE_HIGH = 1
	27
	28	# Clock polarity options
	29	CPOL_0 = 0 # Clock is low when inactive
	30	CPOL_1 = 1 # Clock is high when inactive
	31
	32	# Clock phase options
	33	CPHA_0 = 0 # Data is valid on the leading clock edge
	34	CPHA_1 = 1 # Data is valid on the trailing clock edge
	35
	36	# Bit order options
	37	MSB_FIRST = 0
	38	LSB_FIRST = 1
	39
	40	spi_mode = {
	41	(0, 0): 0, # Mode 0
	42	(0, 1): 1, # Mode 1
	43	(1, 0): 2, # Mode 2
	44	(1, 1): 3, # Mode 3
	45	}
	46
	47	# Annotation formats
	48	ANN_HEX = 0
	49
	50	class Decoder(srd.Decoder):
	51	id = 'spi'
	52	name = 'SPI'
	53	longname = 'Serial Peripheral Interface (SPI) bus'
	54	desc = '...desc...'
	55	longdesc = '...longdesc...'
	56	author = 'Gareth McMullin'
	57	email = 'gareth@blacksphere.co.nz'
	58	license = 'gplv2+'
	59	inputs = ['logic']
	60	outputs = ['spi']
	61	probes = [
	62	{'id': 'mosi', 'name': 'MOSI',
	63	'desc': 'SPI MOSI line (Master out, slave in)'},
	64	{'id': 'miso', 'name': 'MISO',
	65	'desc': 'SPI MISO line (Master in, slave out)'},
	66	{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
	67	{'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
	68	]
	69	options = {
	70	'cs_polarity': ['CS# polarity', ACTIVE_LOW],
	71	'cpol': ['Clock polarity', CPOL_0],
	72	'cpha': ['Clock phase', CPHA_0],
	73	'bitorder': ['Bit order within the SPI data', MSB_FIRST],
	74	'wordsize': ['Word size of SPI data', 8], # 1-64?
	75	}
	76	annotations = [
	77	['Hex', 'SPI data bytes in hex format'],
	78	]
	79
	80	def __init__(self):
	81	self.oldsck = 1
	82	self.bitcount = 0
	83	self.mosidata = 0
	84	self.misodata = 0
	85	self.bytesreceived = 0
	86	self.samplenum = -1
	87	self.cs_was_deasserted_during_data_word = 0
	88
	89	# Set protocol decoder option defaults.
	90	self.cs_polarity = Decoder.options['cs_polarity'][1]
	91	self.cpol = Decoder.options['cpol'][1]
	92	self.cpha = Decoder.options['cpha'][1]
	93	self.bitorder = Decoder.options['bitorder'][1]
	94	self.wordsize = Decoder.options['wordsize'][1]
	95
	96	def start(self, metadata):
	97	self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
	98	self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
	99
	100	def report(self):
	101	return 'SPI: %d bytes received' % self.bytesreceived
	102
	103	def decode(self, ss, es, data):
	104	# HACK! At the moment the number of probes is not handled correctly.
	105	# E.g. if an input file (-i foo.sr) has more than two probes enabled.
	106	# for (samplenum, (mosi, sck, x, y, z, a)) in data:
	107	# for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
	108	for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
	109
	110	self.samplenum += 1 # FIXME
	111
	112	# Ignore sample if the clock pin hasn't changed.
	113	if sck == self.oldsck:
	114	continue
	115
	116	self.oldsck = sck
	117
	118	# Sample data on rising/falling clock edge (depends on mode).
	119	mode = spi_mode[self.cpol, self.cpha]
	120	if mode == 0 and sck == 0: # Sample on rising clock edge
	121	continue
	122	elif mode == 1 and sck == 1: # Sample on falling clock edge
	123	continue
	124	elif mode == 2 and sck == 1: # Sample on falling clock edge
	125	continue
	126	elif mode == 3 and sck == 0: # Sample on rising clock edge
	127	continue
	128
	129	# If this is the first bit, save its sample number.
	130	if self.bitcount == 0:
	131	self.start_sample = samplenum
	132	deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c
	133	if deasserted:
	134	self.cs_was_deasserted_during_data_word = 1
	135
	136	# Receive MOSI bit into our shift register.
	137	if self.bitorder == MSB_FIRST:
	138	self.mosidata \|= mosi << (self.wordsize - 1 - self.bitcount)
	139	else:
	140	self.mosidata \|= mosi << self.bitcount
	141
	142	# Receive MISO bit into our shift register.
	143	if self.bitorder == MSB_FIRST:
	144	self.misodata \|= miso << (self.wordsize - 1 - self.bitcount)
	145	else:
	146	self.misodata \|= miso << self.bitcount
	147
	148	self.bitcount += 1
	149
	150	# Continue to receive if not a byte yet.
	151	if self.bitcount != self.wordsize:
	152	continue
	153
	154	self.put(self.start_sample, self.samplenum, self.out_proto,
	155	['data', self.mosidata, self.misodata])
	156	self.put(self.start_sample, self.samplenum, self.out_ann,
	157	[ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
	158	self.misodata)]])
	159
	160	if self.cs_was_deasserted_during_data_word:
	161	self.put(self.start_sample, self.samplenum, self.out_ann,
	162	[ANN_HEX, ['WARNING: CS# was deasserted during this '
	163	'SPI data byte!']])
	164
	165	# Reset decoder state.
	166	self.mosidata = 0
	167	self.misodata = 0
	168	self.bitcount = 0
	169
	170	# Keep stats for summary.
	171	self.bytesreceived += 1
	172