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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | # Return the specified BCD number (max. 8 bits) as integer. | |
24 | def bcd2int(b): | |
25 | return (b & 0x0f) + ((b >> 4) * 10) | |
26 | ||
27 | class Decoder(srd.Decoder): | |
28 | api_version = 1 | |
29 | id = 'rtc8564' | |
30 | name = 'RTC-8564' | |
31 | longname = 'Epson RTC-8564 JE/NB' | |
32 | desc = 'Realtime clock module protocol.' | |
33 | license = 'gplv2+' | |
34 | inputs = ['i2c'] | |
35 | outputs = ['rtc8564'] | |
36 | probes = [] | |
37 | optional_probes = [ | |
38 | {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'}, | |
39 | {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'}, | |
40 | {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'}, | |
41 | ] | |
42 | options = {} | |
43 | annotations = \ | |
44 | [['reg-0x%02x' % i, 'Register 0x%02x' % i] for i in range(8 + 1)] + [ | |
45 | ['read', 'Read date/time'], | |
46 | ['write', 'Write date/time'], | |
47 | ['bit-reserved', 'Reserved bit'], | |
48 | ['bit-vl', 'VL bit'], | |
49 | ['bit-century', 'Century bit'], | |
50 | ['reg-read', 'Register read'], | |
51 | ['reg-write', 'Register write'], | |
52 | ] | |
53 | annotation_rows = ( | |
54 | ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)), | |
55 | ('regs', 'Register access', (14, 15)), | |
56 | ('date-time', 'Date/time', (9, 10)), | |
57 | ) | |
58 | ||
59 | def __init__(self, **kwargs): | |
60 | self.state = 'IDLE' | |
61 | self.hours = -1 | |
62 | self.minutes = -1 | |
63 | self.seconds = -1 | |
64 | self.days = -1 | |
65 | self.weekdays = -1 | |
66 | self.months = -1 | |
67 | self.years = -1 | |
68 | self.bits = [] | |
69 | ||
70 | def start(self): | |
71 | # self.out_python = self.register(srd.OUTPUT_PYTHON) | |
72 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
73 | ||
74 | def putx(self, data): | |
75 | self.put(self.ss, self.es, self.out_ann, data) | |
76 | ||
77 | def putd(self, bit1, bit2, data): | |
78 | self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data) | |
79 | ||
80 | def putr(self, bit): | |
81 | self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann, | |
82 | [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']]) | |
83 | ||
84 | def handle_reg_0x00(self, b): # Control register 1 | |
85 | pass | |
86 | ||
87 | def handle_reg_0x01(self, b): # Control register 2 | |
88 | ti_tp = 1 if (b & (1 << 4)) else 0 | |
89 | af = 1 if (b & (1 << 3)) else 0 | |
90 | tf = 1 if (b & (1 << 2)) else 0 | |
91 | aie = 1 if (b & (1 << 1)) else 0 | |
92 | tie = 1 if (b & (1 << 0)) else 0 | |
93 | ||
94 | ann = '' | |
95 | ||
96 | s = 'repeated' if ti_tp else 'single-shot' | |
97 | ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\ | |
98 | 'events\n' % (ti_tp, s) | |
99 | s = '' if af else 'no ' | |
100 | ann += 'AF = %d: %salarm interrupt detected\n' % (af, s) | |
101 | s = '' if tf else 'no ' | |
102 | ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s) | |
103 | s = 'enabled' if aie else 'prohibited' | |
104 | ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\ | |
105 | 'occurs\n' % (aie, s) | |
106 | s = 'enabled' if tie else 'prohibited' | |
107 | ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\ | |
108 | 'event occurs\n' % (tie, s) | |
109 | ||
110 | self.putx([1, [ann]]) | |
111 | ||
112 | def handle_reg_0x02(self, b): # Seconds / Voltage-low bit | |
113 | vl = 1 if (b & (1 << 7)) else 0 | |
114 | self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl, | |
115 | 'VL: %d' % vl, 'VL']]) | |
116 | s = self.seconds = bcd2int(b & 0x7f) | |
117 | self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']]) | |
118 | ||
119 | def handle_reg_0x03(self, b): # Minutes | |
120 | self.putr(7) | |
121 | m = self.minutes = bcd2int(b & 0x7f) | |
122 | self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']]) | |
123 | ||
124 | def handle_reg_0x04(self, b): # Hours | |
125 | self.putr(7) | |
126 | self.putr(6) | |
127 | h = self.hours = bcd2int(b & 0x3f) | |
128 | self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']]) | |
129 | ||
130 | def handle_reg_0x05(self, b): # Days | |
131 | self.putr(7) | |
132 | self.putr(6) | |
133 | d = self.days = bcd2int(b & 0x3f) | |
134 | self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']]) | |
135 | ||
136 | def handle_reg_0x06(self, b): # Weekdays | |
137 | for i in (7, 6, 5, 4, 3): | |
138 | self.putr(i) | |
139 | w = self.weekdays = bcd2int(b & 0x07) | |
140 | self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']]) | |
141 | ||
142 | def handle_reg_0x07(self, b): # Months / century bit | |
143 | c = 1 if (b & (1 << 7)) else 0 | |
144 | self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c, | |
145 | 'Cent: %d' % c, 'C: %d' % c, 'C']]) | |
146 | self.putr(6) | |
147 | self.putr(5) | |
148 | m = self.months = bcd2int(b & 0x1f) | |
149 | self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']]) | |
150 | ||
151 | def handle_reg_0x08(self, b): # Years | |
152 | y = self.years = bcd2int(b & 0xff) | |
153 | self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']]) | |
154 | ||
155 | def handle_reg_0x09(self, b): # Alarm, minute | |
156 | pass | |
157 | ||
158 | def handle_reg_0x0a(self, b): # Alarm, hour | |
159 | pass | |
160 | ||
161 | def handle_reg_0x0b(self, b): # Alarm, day | |
162 | pass | |
163 | ||
164 | def handle_reg_0x0c(self, b): # Alarm, weekday | |
165 | pass | |
166 | ||
167 | def handle_reg_0x0d(self, b): # CLKOUT output | |
168 | pass | |
169 | ||
170 | def handle_reg_0x0e(self, b): # Timer setting | |
171 | pass | |
172 | ||
173 | def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer | |
174 | pass | |
175 | ||
176 | def decode(self, ss, es, data): | |
177 | cmd, databyte = data | |
178 | ||
179 | # Collect the 'BITS' packet, then return. The next packet is | |
180 | # guaranteed to belong to these bits we just stored. | |
181 | if cmd == 'BITS': | |
182 | self.bits = databyte | |
183 | return | |
184 | ||
185 | # Store the start/end samples of this I²C packet. | |
186 | self.ss, self.es = ss, es | |
187 | ||
188 | # State machine. | |
189 | if self.state == 'IDLE': | |
190 | # Wait for an I²C START condition. | |
191 | if cmd != 'START': | |
192 | return | |
193 | self.state = 'GET SLAVE ADDR' | |
194 | self.block_start_sample = ss | |
195 | elif self.state == 'GET SLAVE ADDR': | |
196 | # Wait for an address write operation. | |
197 | # TODO: We should only handle packets to the RTC slave (0xa2/0xa3). | |
198 | if cmd != 'ADDRESS WRITE': | |
199 | return | |
200 | self.state = 'GET REG ADDR' | |
201 | elif self.state == 'GET REG ADDR': | |
202 | # Wait for a data write (master selects the slave register). | |
203 | if cmd != 'DATA WRITE': | |
204 | return | |
205 | self.reg = databyte | |
206 | self.state = 'WRITE RTC REGS' | |
207 | elif self.state == 'WRITE RTC REGS': | |
208 | # If we see a Repeated Start here, it's probably an RTC read. | |
209 | if cmd == 'START REPEAT': | |
210 | self.state = 'READ RTC REGS' | |
211 | return | |
212 | # Otherwise: Get data bytes until a STOP condition occurs. | |
213 | if cmd == 'DATA WRITE': | |
214 | r, s = self.reg, '%02X: %02X' % (self.reg, databyte) | |
215 | self.putx([15, ['Write register %s' % s, 'Write reg %s' % s, | |
216 | 'WR %s' % s, 'WR', 'W']]) | |
217 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
218 | handle_reg(databyte) | |
219 | self.reg += 1 | |
220 | # TODO: Check for NACK! | |
221 | elif cmd == 'STOP': | |
222 | # TODO: Handle read/write of only parts of these items. | |
223 | d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, | |
224 | self.years, self.hours, self.minutes, self.seconds) | |
225 | self.put(self.block_start_sample, es, self.out_ann, | |
226 | [9, ['Write date/time: %s' % d, 'Write: %s' % d, | |
227 | 'W: %s' % d]]) | |
228 | self.state = 'IDLE' | |
229 | else: | |
230 | pass # TODO | |
231 | elif self.state == 'READ RTC REGS': | |
232 | # Wait for an address read operation. | |
233 | # TODO: We should only handle packets to the RTC slave (0xa2/0xa3). | |
234 | if cmd == 'ADDRESS READ': | |
235 | self.state = 'READ RTC REGS2' | |
236 | return | |
237 | else: | |
238 | pass # TODO | |
239 | elif self.state == 'READ RTC REGS2': | |
240 | if cmd == 'DATA READ': | |
241 | r, s = self.reg, '%02X: %02X' % (self.reg, databyte) | |
242 | self.putx([15, ['Read register %s' % s, 'Read reg %s' % s, | |
243 | 'RR %s' % s, 'RR', 'R']]) | |
244 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
245 | handle_reg(databyte) | |
246 | self.reg += 1 | |
247 | # TODO: Check for NACK! | |
248 | elif cmd == 'STOP': | |
249 | d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, | |
250 | self.years, self.hours, self.minutes, self.seconds) | |
251 | self.put(self.block_start_sample, es, self.out_ann, | |
252 | [10, ['Read date/time: %s' % d, 'Read: %s' % d, | |
253 | 'R: %s' % d]]) | |
254 | self.state = 'IDLE' | |
255 | else: | |
256 | pass # TODO? | |
257 | else: | |
258 | raise Exception('Invalid state: %s' % self.state) | |
259 |