[libsigrokdecode.git] / decoders / rtc8564 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd
from common.srdhelper import bcd2int

def reg_list():
    l = []
    for i in range(8 + 1):
        l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))

    return tuple(l)

class Decoder(srd.Decoder):
    api_version = 3
    id = 'rtc8564'
    name = 'RTC-8564'
    longname = 'Epson RTC-8564 JE/NB'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['rtc8564']
    annotations = reg_list() + (
        ('read', 'Read date/time'),
        ('write', 'Write date/time'),
        ('bit-reserved', 'Reserved bit'),
        ('bit-vl', 'VL bit'),
        ('bit-century', 'Century bit'),
        ('reg-read', 'Register read'),
        ('reg-write', 'Register write'),
    )
    annotation_rows = (
        ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
        ('regs', 'Register access', (14, 15)),
        ('date-time', 'Date/time', (9, 10)),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.weekdays = -1
        self.months = -1
        self.years = -1
        self.bits = []

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putd(self, bit1, bit2, data):
        self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)

    def putr(self, bit):
        self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
                 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])

    def handle_reg_0x00(self, b): # Control register 1
        pass

    def handle_reg_0x01(self, b): # Control register 2
        ti_tp = 1 if (b & (1 << 4)) else 0
        af = 1 if (b & (1 << 3)) else 0
        tf = 1 if (b & (1 << 2)) else 0
        aie = 1 if (b & (1 << 1)) else 0
        tie = 1 if (b & (1 << 0)) else 0

        ann = ''

        s = 'repeated' if ti_tp else 'single-shot'
        ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
               'events\n' % (ti_tp, s)
        s = '' if af else 'no '
        ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
        s = '' if tf else 'no '
        ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
        s = 'enabled' if aie else 'prohibited'
        ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
               'occurs\n' % (aie, s)
        s = 'enabled' if tie else 'prohibited'
        ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
               'event occurs\n' % (tie, s)

        self.putx([1, [ann]])

    def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
        vl = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
                        'VL: %d' % vl, 'VL']])
        s = self.seconds = bcd2int(b & 0x7f)
        self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])

    def handle_reg_0x03(self, b): # Minutes
        self.putr(7)
        m = self.minutes = bcd2int(b & 0x7f)
        self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x04(self, b): # Hours
        self.putr(7)
        self.putr(6)
        h = self.hours = bcd2int(b & 0x3f)
        self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])

    def handle_reg_0x05(self, b): # Days
        self.putr(7)
        self.putr(6)
        d = self.days = bcd2int(b & 0x3f)
        self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])

    def handle_reg_0x06(self, b): # Weekdays
        for i in (7, 6, 5, 4, 3):
            self.putr(i)
        w = self.weekdays = bcd2int(b & 0x07)
        self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])

    def handle_reg_0x07(self, b): # Months / century bit
        c = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
                              'Cent: %d' % c, 'C: %d' % c, 'C']])
        self.putr(6)
        self.putr(5)
        m = self.months = bcd2int(b & 0x1f)
        self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x08(self, b): # Years
        y = self.years = bcd2int(b & 0xff)
        self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])

    def handle_reg_0x09(self, b): # Alarm, minute
        pass

    def handle_reg_0x0a(self, b): # Alarm, hour
        pass

    def handle_reg_0x0b(self, b): # Alarm, day
        pass

    def handle_reg_0x0c(self, b): # Alarm, weekday
        pass

    def handle_reg_0x0d(self, b): # CLKOUT output
        pass

    def handle_reg_0x0e(self, b): # Timer setting
        pass

    def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
        pass

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Collect the 'BITS' packet, then return. The next packet is
        # guaranteed to belong to these bits we just stored.
        if cmd == 'BITS':
            self.bits = databyte
            return

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.ss_block = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd != 'ADDRESS WRITE':
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's probably an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
                self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
                                'WR %s' % s, 'WR', 'W']])
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                # TODO: Handle read/write of only parts of these items.
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.ss_block, es, self.out_ann,
                         [9, ['Write date/time: %s' % d, 'Write: %s' % d,
                              'W: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd == 'ADDRESS READ':
                self.state = 'READ RTC REGS2'
                return
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
                self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
                                'RR %s' % s, 'RR', 'R']])
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.ss_block, es, self.out_ann,
                         [10, ['Read date/time: %s' % d, 'Read: %s' % d,
                               'R: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO?
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
	21	from common.srdhelper import bcd2int
	22
	23	def reg_list():
	24	l = []
	25	for i in range(8 + 1):
	26	l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))
	27
	28	return tuple(l)
	29
	30	class Decoder(srd.Decoder):
	31	api_version = 3
	32	id = 'rtc8564'
	33	name = 'RTC-8564'
	34	longname = 'Epson RTC-8564 JE/NB'
	35	desc = 'Realtime clock module protocol.'
	36	license = 'gplv2+'
	37	inputs = ['i2c']
	38	outputs = ['rtc8564']
	39	annotations = reg_list() + (
	40	('read', 'Read date/time'),
	41	('write', 'Write date/time'),
	42	('bit-reserved', 'Reserved bit'),
	43	('bit-vl', 'VL bit'),
	44	('bit-century', 'Century bit'),
	45	('reg-read', 'Register read'),
	46	('reg-write', 'Register write'),
	47	)
	48	annotation_rows = (
	49	('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
	50	('regs', 'Register access', (14, 15)),
	51	('date-time', 'Date/time', (9, 10)),
	52	)
	53
	54	def __init__(self):
	55	self.reset()
	56
	57	def reset(self):
	58	self.state = 'IDLE'
	59	self.hours = -1
	60	self.minutes = -1
	61	self.seconds = -1
	62	self.days = -1
	63	self.weekdays = -1
	64	self.months = -1
	65	self.years = -1
	66	self.bits = []
	67
	68	def start(self):
	69	self.out_ann = self.register(srd.OUTPUT_ANN)
	70
	71	def putx(self, data):
	72	self.put(self.ss, self.es, self.out_ann, data)
	73
	74	def putd(self, bit1, bit2, data):
	75	self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
	76
	77	def putr(self, bit):
	78	self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
	79	[11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
	80
	81	def handle_reg_0x00(self, b): # Control register 1
	82	pass
	83
	84	def handle_reg_0x01(self, b): # Control register 2
	85	ti_tp = 1 if (b & (1 << 4)) else 0
	86	af = 1 if (b & (1 << 3)) else 0
	87	tf = 1 if (b & (1 << 2)) else 0
	88	aie = 1 if (b & (1 << 1)) else 0
	89	tie = 1 if (b & (1 << 0)) else 0
	90
	91	ann = ''
	92
	93	s = 'repeated' if ti_tp else 'single-shot'
	94	ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
	95	'events\n' % (ti_tp, s)
	96	s = '' if af else 'no '
	97	ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
	98	s = '' if tf else 'no '
	99	ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
	100	s = 'enabled' if aie else 'prohibited'
	101	ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
	102	'occurs\n' % (aie, s)
	103	s = 'enabled' if tie else 'prohibited'
	104	ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
	105	'event occurs\n' % (tie, s)
	106
	107	self.putx([1, [ann]])
	108
	109	def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
	110	vl = 1 if (b & (1 << 7)) else 0
	111	self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
	112	'VL: %d' % vl, 'VL']])
	113	s = self.seconds = bcd2int(b & 0x7f)
	114	self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
	115
	116	def handle_reg_0x03(self, b): # Minutes
	117	self.putr(7)
	118	m = self.minutes = bcd2int(b & 0x7f)
	119	self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
	120
	121	def handle_reg_0x04(self, b): # Hours
	122	self.putr(7)
	123	self.putr(6)
	124	h = self.hours = bcd2int(b & 0x3f)
	125	self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
	126
	127	def handle_reg_0x05(self, b): # Days
	128	self.putr(7)
	129	self.putr(6)
	130	d = self.days = bcd2int(b & 0x3f)
	131	self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
	132
	133	def handle_reg_0x06(self, b): # Weekdays
	134	for i in (7, 6, 5, 4, 3):
	135	self.putr(i)
	136	w = self.weekdays = bcd2int(b & 0x07)
	137	self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
	138
	139	def handle_reg_0x07(self, b): # Months / century bit
	140	c = 1 if (b & (1 << 7)) else 0
	141	self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
	142	'Cent: %d' % c, 'C: %d' % c, 'C']])
	143	self.putr(6)
	144	self.putr(5)
	145	m = self.months = bcd2int(b & 0x1f)
	146	self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
	147
	148	def handle_reg_0x08(self, b): # Years
	149	y = self.years = bcd2int(b & 0xff)
	150	self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
	151
	152	def handle_reg_0x09(self, b): # Alarm, minute
	153	pass
	154
	155	def handle_reg_0x0a(self, b): # Alarm, hour
	156	pass
	157
	158	def handle_reg_0x0b(self, b): # Alarm, day
	159	pass
	160
	161	def handle_reg_0x0c(self, b): # Alarm, weekday
	162	pass
	163
	164	def handle_reg_0x0d(self, b): # CLKOUT output
	165	pass
	166
	167	def handle_reg_0x0e(self, b): # Timer setting
	168	pass
	169
	170	def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
	171	pass
	172
	173	def decode(self, ss, es, data):
	174	cmd, databyte = data
	175
	176	# Collect the 'BITS' packet, then return. The next packet is
	177	# guaranteed to belong to these bits we just stored.
	178	if cmd == 'BITS':
	179	self.bits = databyte
	180	return
	181
	182	# Store the start/end samples of this I²C packet.
	183	self.ss, self.es = ss, es
	184
	185	# State machine.
	186	if self.state == 'IDLE':
	187	# Wait for an I²C START condition.
	188	if cmd != 'START':
	189	return
	190	self.state = 'GET SLAVE ADDR'
	191	self.ss_block = ss
	192	elif self.state == 'GET SLAVE ADDR':
	193	# Wait for an address write operation.
	194	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	195	if cmd != 'ADDRESS WRITE':
	196	return
	197	self.state = 'GET REG ADDR'
	198	elif self.state == 'GET REG ADDR':
	199	# Wait for a data write (master selects the slave register).
	200	if cmd != 'DATA WRITE':
	201	return
	202	self.reg = databyte
	203	self.state = 'WRITE RTC REGS'
	204	elif self.state == 'WRITE RTC REGS':
	205	# If we see a Repeated Start here, it's probably an RTC read.
	206	if cmd == 'START REPEAT':
	207	self.state = 'READ RTC REGS'
	208	return
	209	# Otherwise: Get data bytes until a STOP condition occurs.
	210	if cmd == 'DATA WRITE':
	211	r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
	212	self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
	213	'WR %s' % s, 'WR', 'W']])
	214	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	215	handle_reg(databyte)
	216	self.reg += 1
	217	# TODO: Check for NACK!
	218	elif cmd == 'STOP':
	219	# TODO: Handle read/write of only parts of these items.
	220	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	221	self.years, self.hours, self.minutes, self.seconds)
	222	self.put(self.ss_block, es, self.out_ann,
	223	[9, ['Write date/time: %s' % d, 'Write: %s' % d,
	224	'W: %s' % d]])
	225	self.state = 'IDLE'
	226	else:
	227	pass # TODO
	228	elif self.state == 'READ RTC REGS':
	229	# Wait for an address read operation.
	230	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	231	if cmd == 'ADDRESS READ':
	232	self.state = 'READ RTC REGS2'
	233	return
	234	else:
	235	pass # TODO
	236	elif self.state == 'READ RTC REGS2':
	237	if cmd == 'DATA READ':
	238	r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
	239	self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
	240	'RR %s' % s, 'RR', 'R']])
	241	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	242	handle_reg(databyte)
	243	self.reg += 1
	244	# TODO: Check for NACK!
	245	elif cmd == 'STOP':
	246	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	247	self.years, self.hours, self.minutes, self.seconds)
	248	self.put(self.ss_block, es, self.out_ann,
	249	[10, ['Read date/time: %s' % d, 'Read: %s' % d,
	250	'R: %s' % d]])
	251	self.state = 'IDLE'
	252	else:
	253	pass # TODO?