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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2012 Iztok Jeras <iztok.jeras@gmail.com>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, see <http://www.gnu.org/licenses/>.
18##
19
20import sigrokdecode as srd
21
22# Dictionary of ROM commands and their names, next state.
23command = {
24 0x33: ['Read ROM' , 'GET ROM' ],
25 0x0f: ['Conditional read ROM' , 'GET ROM' ],
26 0xcc: ['Skip ROM' , 'TRANSPORT' ],
27 0x55: ['Match ROM' , 'GET ROM' ],
28 0xf0: ['Search ROM' , 'SEARCH ROM'],
29 0xec: ['Conditional search ROM', 'SEARCH ROM'],
30 0x3c: ['Overdrive skip ROM' , 'TRANSPORT' ],
31 0x69: ['Overdrive match ROM' , 'GET ROM' ],
32}
33
34class Decoder(srd.Decoder):
35 api_version = 3
36 id = 'onewire_network'
37 name = '1-Wire network layer'
38 longname = '1-Wire serial communication bus (network layer)'
39 desc = 'Bidirectional, half-duplex, asynchronous serial bus.'
40 license = 'gplv2+'
41 inputs = ['onewire_link']
42 outputs = ['onewire_network']
43 tags = ['Embedded/industrial']
44 annotations = (
45 ('text', 'Human-readable text'),
46 )
47
48 def __init__(self):
49 self.reset()
50
51 def reset(self):
52 self.ss_block = 0
53 self.es_block = 0
54 self.state = 'COMMAND'
55 self.bit_cnt = 0
56 self.search = 'P'
57 self.data_p = 0x0
58 self.data_n = 0x0
59 self.data = 0x0
60 self.rom = 0x0000000000000000
61
62 def start(self):
63 self.out_python = self.register(srd.OUTPUT_PYTHON)
64 self.out_ann = self.register(srd.OUTPUT_ANN)
65
66 def putx(self, data):
67 # Helper function for most annotations.
68 self.put(self.ss_block, self.es_block, self.out_ann, data)
69
70 def puty(self, data):
71 # Helper function for most protocol packets.
72 self.put(self.ss_block, self.es_block, self.out_python, data)
73
74 def decode(self, ss, es, data):
75 code, val = data
76
77 # State machine.
78 if code == 'RESET/PRESENCE':
79 self.search = 'P'
80 self.bit_cnt = 0
81 self.put(ss, es, self.out_ann,
82 [0, ['Reset/presence: %s' % ('true' if val else 'false')]])
83 self.put(ss, es, self.out_python, ['RESET/PRESENCE', val])
84 self.state = 'COMMAND'
85 return
86
87 # For now we're only interested in 'RESET/PRESENCE' and 'BIT' packets.
88 if code != 'BIT':
89 return
90
91 if self.state == 'COMMAND':
92 # Receiving and decoding a ROM command.
93 if self.onewire_collect(8, val, ss, es) == 0:
94 return
95 if self.data in command:
96 self.putx([0, ['ROM command: 0x%02x \'%s\''
97 % (self.data, command[self.data][0])]])
98 self.state = command[self.data][1]
99 else:
100 self.putx([0, ['ROM command: 0x%02x \'%s\''
101 % (self.data, 'unrecognized')]])
102 self.state = 'COMMAND ERROR'
103 elif self.state == 'GET ROM':
104 # A 64 bit device address is selected.
105 # Family code (1 byte) + serial number (6 bytes) + CRC (1 byte)
106 if self.onewire_collect(64, val, ss, es) == 0:
107 return
108 self.rom = self.data & 0xffffffffffffffff
109 self.putx([0, ['ROM: 0x%016x' % self.rom]])
110 self.puty(['ROM', self.rom])
111 self.state = 'TRANSPORT'
112 elif self.state == 'SEARCH ROM':
113 # A 64 bit device address is searched for.
114 # Family code (1 byte) + serial number (6 bytes) + CRC (1 byte)
115 if self.onewire_search(64, val, ss, es) == 0:
116 return
117 self.rom = self.data & 0xffffffffffffffff
118 self.putx([0, ['ROM: 0x%016x' % self.rom]])
119 self.puty(['ROM', self.rom])
120 self.state = 'TRANSPORT'
121 elif self.state == 'TRANSPORT':
122 # The transport layer is handled in byte sized units.
123 if self.onewire_collect(8, val, ss, es) == 0:
124 return
125 self.putx([0, ['Data: 0x%02x' % self.data]])
126 self.puty(['DATA', self.data])
127 elif self.state == 'COMMAND ERROR':
128 # Since the command is not recognized, print raw data.
129 if self.onewire_collect(8, val, ss, es) == 0:
130 return
131 self.putx([0, ['ROM error data: 0x%02x' % self.data]])
132
133 # Data collector.
134 def onewire_collect(self, length, val, ss, es):
135 # Storing the sample this sequence begins with.
136 if self.bit_cnt == 0:
137 self.ss_block = ss
138 self.data = self.data & ~(1 << self.bit_cnt) | (val << self.bit_cnt)
139 self.bit_cnt += 1
140 # Storing the sample this sequence ends with.
141 # In case the full length of the sequence is received, return 1.
142 if self.bit_cnt == length:
143 self.es_block = es
144 self.data = self.data & ((1 << length) - 1)
145 self.bit_cnt = 0
146 return 1
147 else:
148 return 0
149
150 # Search collector.
151 def onewire_search(self, length, val, ss, es):
152 # Storing the sample this sequence begins with.
153 if (self.bit_cnt == 0) and (self.search == 'P'):
154 self.ss_block = ss
155
156 if self.search == 'P':
157 # Master receives an original address bit.
158 self.data_p = self.data_p & ~(1 << self.bit_cnt) | \
159 (val << self.bit_cnt)
160 self.search = 'N'
161 elif self.search == 'N':
162 # Master receives a complemented address bit.
163 self.data_n = self.data_n & ~(1 << self.bit_cnt) | \
164 (val << self.bit_cnt)
165 self.search = 'D'
166 elif self.search == 'D':
167 # Master transmits an address bit.
168 self.data = self.data & ~(1 << self.bit_cnt) | (val << self.bit_cnt)
169 self.search = 'P'
170 self.bit_cnt += 1
171
172 # Storing the sample this sequence ends with.
173 # In case the full length of the sequence is received, return 1.
174 if self.bit_cnt == length:
175 self.es_block = es
176 self.data_p = self.data_p & ((1 << length) - 1)
177 self.data_n = self.data_n & ((1 << length) - 1)
178 self.data = self.data & ((1 << length) - 1)
179 self.search = 'P'
180 self.bit_cnt = 0
181 return 1
182 else:
183 return 0