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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | # Definitions of various bits in MXC6225XU registers. | |
24 | status = { | |
25 | # SH[1:0] | |
26 | 'sh': { | |
27 | 0b00: 'none', | |
28 | 0b01: 'shake left', | |
29 | 0b10: 'shake right', | |
30 | 0b11: 'undefined', | |
31 | }, | |
32 | # ORI[1:0] and OR[1:0] (same format) | |
33 | 'ori': { | |
34 | 0b00: 'vertical in upright orientation', | |
35 | 0b01: 'rotated 90 degrees clockwise', | |
36 | 0b10: 'vertical in inverted orientation', | |
37 | 0b11: 'rotated 90 degrees counterclockwise', | |
38 | }, | |
39 | # SHTH[1:0] | |
40 | 'shth': { | |
41 | 0b00: '0.5g', | |
42 | 0b01: '1.0g', | |
43 | 0b10: '1.5g', | |
44 | 0b11: '2.0g', | |
45 | }, | |
46 | # SHC[1:0] | |
47 | 'shc': { | |
48 | 0b00: '16', | |
49 | 0b01: '32', | |
50 | 0b10: '64', | |
51 | 0b11: '128', | |
52 | }, | |
53 | # ORC[1:0] | |
54 | 'orc': { | |
55 | 0b00: '16', | |
56 | 0b01: '32', | |
57 | 0b10: '64', | |
58 | 0b11: '128', | |
59 | }, | |
60 | } | |
61 | ||
62 | class Decoder(srd.Decoder): | |
63 | api_version = 1 | |
64 | id = 'mxc6225xu' | |
65 | name = 'MXC6225XU' | |
66 | longname = 'MEMSIC MXC6225XU' | |
67 | desc = 'Digital Thermal Orientation Sensor (DTOS) protocol.' | |
68 | license = 'gplv2+' | |
69 | inputs = ['i2c'] | |
70 | outputs = ['mxc6225xu'] | |
71 | optional_probes = ( | |
72 | {'id': 'int', 'name': 'INT', 'desc': 'DTOS interrupt output pin'}, | |
73 | ) | |
74 | annotations = ( | |
75 | ('text', 'Human-readable text'), | |
76 | ) | |
77 | ||
78 | def __init__(self, **kwargs): | |
79 | self.state = 'IDLE' | |
80 | ||
81 | def start(self): | |
82 | # self.out_python = self.register(srd.OUTPUT_PYTHON) | |
83 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
84 | ||
85 | def putx(self, data): | |
86 | self.put(self.ss, self.es, self.out_ann, data) | |
87 | ||
88 | def handle_reg_0x00(self, b): | |
89 | # XOUT: 8-bit x-axis acceleration output. | |
90 | # Data is in 2's complement, values range from -128 to 127. | |
91 | self.putx([0, ['XOUT: %d' % b]]) | |
92 | ||
93 | def handle_reg_0x01(self, b): | |
94 | # YOUT: 8-bit y-axis acceleration output. | |
95 | # Data is in 2's complement, values range from -128 to 127. | |
96 | self.putx([0, ['YOUT: %d' % b]]) | |
97 | ||
98 | def handle_reg_0x02(self, b): | |
99 | # STATUS: Orientation and shake status. | |
100 | ||
101 | # Bits[7:7]: INT | |
102 | int_val = (b >> 7) & 1 | |
103 | s = 'unchanged and no' if (int_val == 0) else 'changed or' | |
104 | ann = 'INT = %d: Orientation %s shake event occured\n' % (int_val, s) | |
105 | ||
106 | # Bits[6:5]: SH[1:0] | |
107 | sh = (((b >> 6) & 1) << 1) | ((b >> 5) & 1) | |
108 | ann += 'SH[1:0] = %s: Shake event: %s\n' % \ | |
109 | (bin(sh)[2:], status['sh'][sh]) | |
110 | ||
111 | # Bits[4:4]: TILT | |
112 | tilt = (b >> 4) & 1 | |
113 | s = '' if (tilt == 0) else 'not ' | |
114 | ann += 'TILT = %d: Orientation measurement is %svalid\n' % (tilt, s) | |
115 | ||
116 | # Bits[3:2]: ORI[1:0] | |
117 | ori = (((b >> 3) & 1) << 1) | ((b >> 2) & 1) | |
118 | ann += 'ORI[1:0] = %s: %s\n' % (bin(ori)[2:], status['ori'][ori]) | |
119 | ||
120 | # Bits[1:0]: OR[1:0] | |
121 | or_val = (((b >> 1) & 1) << 1) | ((b >> 0) & 1) | |
122 | ann += 'OR[1:0] = %s: %s\n' % (bin(or_val)[2:], status['ori'][or_val]) | |
123 | ||
124 | # ann += 'b = %s\n' % (bin(b)) | |
125 | ||
126 | self.putx([0, [ann]]) | |
127 | ||
128 | def handle_reg_0x03(self, b): | |
129 | # DETECTION: Powerdown, orientation and shake detection parameters. | |
130 | # Note: This is a write-only register. | |
131 | ||
132 | # Bits[7:7]: PD | |
133 | pd = (b >> 7) & 1 | |
134 | s = 'Do not power down' if (pd == 0) else 'Power down' | |
135 | ann = 'PD = %d: %s the device (into a low-power state)\n' % (pd, s) | |
136 | ||
137 | # Bits[6:6]: SHM | |
138 | shm = (b >> 6) & 1 | |
139 | ann = 'SHM = %d: Set shake mode to %d\n' % (shm, shm) | |
140 | ||
141 | # Bits[5:4]: SHTH[1:0] | |
142 | shth = (((b >> 5) & 1) << 1) | ((b >> 4) & 1) | |
143 | ann += 'SHTH[1:0] = %s: Set shake threshold to %s\n' \ | |
144 | % (bin(shth)[2:], status['shth'][shth]) | |
145 | ||
146 | # Bits[3:2]: SHC[1:0] | |
147 | shc = (((b >> 3) & 1) << 1) | ((b >> 2) & 1) | |
148 | ann += 'SHC[1:0] = %s: Set shake count to %s readings\n' \ | |
149 | % (bin(shc)[2:], status['shc'][shc]) | |
150 | ||
151 | # Bits[1:0]: ORC[1:0] | |
152 | orc = (((b >> 1) & 1) << 1) | ((b >> 0) & 1) | |
153 | ann += 'ORC[1:0] = %s: Set orientation count to %s readings\n' \ | |
154 | % (bin(orc)[2:], status['orc'][orc]) | |
155 | ||
156 | self.putx([0, [ann]]) | |
157 | ||
158 | # TODO: Fixup, this is copy-pasted from another PD. | |
159 | # TODO: Handle/check the ACKs/NACKs. | |
160 | def decode(self, ss, es, data): | |
161 | cmd, databyte = data | |
162 | ||
163 | # Store the start/end samples of this I²C packet. | |
164 | self.ss, self.es = ss, es | |
165 | ||
166 | # State machine. | |
167 | if self.state == 'IDLE': | |
168 | # Wait for an I²C START condition. | |
169 | if cmd != 'START': | |
170 | return | |
171 | self.state = 'GET SLAVE ADDR' | |
172 | self.block_start_sample = ss | |
173 | elif self.state == 'GET SLAVE ADDR': | |
174 | # Wait for an address write operation. | |
175 | # TODO: We should only handle packets to the slave(?) | |
176 | if cmd != 'ADDRESS WRITE': | |
177 | return | |
178 | self.state = 'GET REG ADDR' | |
179 | elif self.state == 'GET REG ADDR': | |
180 | # Wait for a data write (master selects the slave register). | |
181 | if cmd != 'DATA WRITE': | |
182 | return | |
183 | self.reg = databyte | |
184 | self.state = 'WRITE REGS' | |
185 | elif self.state == 'WRITE REGS': | |
186 | # If we see a Repeated Start here, it's a multi-byte read. | |
187 | if cmd == 'START REPEAT': | |
188 | self.state = 'READ REGS' | |
189 | return | |
190 | # Otherwise: Get data bytes until a STOP condition occurs. | |
191 | if cmd == 'DATA WRITE': | |
192 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
193 | handle_reg(databyte) | |
194 | self.reg += 1 | |
195 | # TODO: Check for NACK! | |
196 | elif cmd == 'STOP': | |
197 | # TODO | |
198 | self.state = 'IDLE' | |
199 | else: | |
200 | pass # TODO | |
201 | elif self.state == 'READ REGS': | |
202 | # Wait for an address read operation. | |
203 | # TODO: We should only handle packets to the slave(?) | |
204 | if cmd == 'ADDRESS READ': | |
205 | self.state = 'READ REGS2' | |
206 | return | |
207 | else: | |
208 | pass # TODO | |
209 | elif self.state == 'READ REGS2': | |
210 | if cmd == 'DATA READ': | |
211 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
212 | handle_reg(databyte) | |
213 | self.reg += 1 | |
214 | # TODO: Check for NACK! | |
215 | elif cmd == 'STOP': | |
216 | # TODO | |
217 | self.state = 'IDLE' | |
218 | else: | |
219 | pass # TODO? | |
220 | else: | |
221 | raise Exception('Invalid state: %s' % self.state) | |
222 |