[libsigrokdecode.git] / decoders / maple_bus / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2017 Marcus Comstedt <marcus@mc.pp.se>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd

ann = [
    ['Size', 'L'],
    ['SrcAP', 'S'],
    ['DstAP', 'D'],
    ['Cmd', 'C'],
    ['Data'],
    ['Cksum', 'K'],
]

class Decoder(srd.Decoder):
    api_version = 3
    id = 'maple_bus'
    name = 'Maple bus'
    longname = 'SEGA Maple bus'
    desc = 'Maple bus peripheral protocol for SEGA Dreamcast.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['maple_bus']
    channels = (
        {'id': 'sdcka', 'name': 'SDCKA', 'desc': 'Data/clock line A'},
        {'id': 'sdckb', 'name': 'SDCKB', 'desc': 'Data/clock line B'},
    )
    annotations = (
        ('start', 'Start pattern'),
        ('end', 'End pattern'),
        ('start-with-crc', 'Start pattern with CRC'),
        ('occupancy', 'SDCKB occupancy pattern'),
        ('reset', 'RESET pattern'),
        ('bit', 'Bit'),
        ('size', 'Data size'),
        ('source', 'Source AP'),
        ('dest', 'Destination AP'),
        ('command', 'Command'),
        ('data', 'Data'),
        ('checksum', 'Checksum'),
        ('frame-error', 'Frame error'),
        ('checksum-error', 'Checksum error'),
        ('size-error', 'Size error'),
    )
    annotation_rows = (
        ('bits', 'Bits', (0, 1, 2, 3, 4, 5)),
        ('fields', 'Fields', (6, 7, 8, 9, 10, 11)),
        ('warnings', 'Warnings', (12, 13, 14)),
    )
    binary = (
        ('size', 'Data size'),
        ('source', 'Source AP'),
        ('dest', 'Destination AP'),
        ('command', 'Command code'),
        ('data', 'Data'),
        ('checksum', 'Checksum'),
    )

    def __init__(self):
        pass

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)
        self.out_binary = self.register(srd.OUTPUT_BINARY)
        self.pending_bit_pos = None

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putb(self, data):
        self.put(self.ss, self.es, self.out_binary, data)

    def byte_annotation(self, bintype, d):
        return [bintype + 6,
            ['%s: %02X' % (name, d) for name in ann[bintype]] + ['%02X' % d]]

    def got_start(self):
        self.putx([0, ['Start pattern', 'Start', 'S']])

    def got_end(self):
        self.putx([1, ['End pattern', 'End', 'E']])
        if self.length != self.expected_length + 1:
            self.putx([14, ['Size error', 'L error', 'LE']])

    def got_start_with_crc(self):
        self.putx([2, ['Start pattern with CRC', 'Start CRC', 'SC']])

    def got_occupancy(self):
        self.putx([3, ['SDCKB occupancy pattern', 'Occupancy', 'O']])

    def got_reset(self):
        self.putx([4, ['RESET pattern', 'RESET', 'R']])

    def output_pending_bit(self):
        if self.pending_bit_pos:
            self.put(self.pending_bit_pos, self.pending_bit_pos, self.out_ann, [5, ['Bit: %d' % self.pending_bit, '%d' % self.pending_bit]])

    def got_bit(self, n):
        self.output_pending_bit()
        self.data = self.data * 2 + n
        self.pending_bit = n
        self.pending_bit_pos = self.samplenum

    def got_byte(self):
        self.output_pending_bit()
        bintype = 4
        if self.length < 4:
            if self.length == 0:
                self.expected_length = 4 * (self.data + 1)
            bintype = self.length
        elif self.length == self.expected_length:
            bintype = 5
            if self.data != self.checksum:
                self.putx([13, ['Cksum error', 'K error', 'KE']])
        self.length = self.length + 1
        self.checksum = self.checksum ^ self.data
        self.putx(self.byte_annotation(bintype, self.data))
        self.putb([bintype, bytes([self.data])])
        self.pending_bit_pos = None

    def frame_error(self):
        self.putx([7, ['Frame error', 'F error', 'FE']])

    def handle_start(self):
        self.wait({0: 'l', 1: 'h'})
        self.ss = self.samplenum
        count = 0
        while True:
            sdcka, sdckb = self.wait([{1: 'f'}, {0: 'r'}])
            if self.matched[0]:
                count = count + 1
            if self.matched[1]:
                self.es = self.samplenum
                if sdckb == 1:
                    if count == 4:
                        self.got_start()
                        return True
                    elif count == 6:
                        self.got_start_with_crc()
                        return True
                    elif count == 8:
                        self.got_occupancy()
                        return False
                    elif count >= 14:
                        self.got_reset()
                        return False
                self.frame_error()
                return False

    def handle_byte_or_stop(self):
        self.ss = self.samplenum
        self.pending_bit_pos = None
        initial = True
        counta = 0
        countb = 0
        self.data = 0
        while countb < 4:
            sdcka, sdckb = self.wait([{0: 'f'}, {1: 'f'}])
            self.es = self.samplenum
            if self.matched[0]:
                if counta == countb:
                    self.got_bit(sdckb)
                    counta = counta + 1
                elif counta == 1 and countb == 0 and self.data == 0 and sdckb == 0:
                    self.wait([{0: 'h', 1: 'h'}, {0: 'f'}, {1: 'f'}])
                    self.es = self.samplenum
                    if self.matched[0]:
                        self.got_end()
                    else:
                        self.frame_error()
                    return False
                else:
                    self.frame_error()
                    return False
            elif self.matched[1]:
                if counta == countb + 1:
                    self.got_bit(sdcka)
                    countb = countb + 1
                elif counta == 0 and countb == 0 and sdcka == 1 and initial:
                    self.ss = self.samplenum
                    initial = False
                else:
                    self.frame_error()
                    return False
        self.wait({0: 'h'})
        self.es = self.samplenum
        self.got_byte()
        return True

    def decode(self):
        while True:
            while not self.handle_start():
                pass
            self.length = 0
            self.expected_length = 4
            self.checksum = 0
            while self.handle_byte_or_stop():
                pass
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2017 Marcus Comstedt <marcus@mc.pp.se>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
	21
	22	ann = [
	23	['Size', 'L'],
	24	['SrcAP', 'S'],
	25	['DstAP', 'D'],
	26	['Cmd', 'C'],
	27	['Data'],
	28	['Cksum', 'K'],
	29	]
	30
	31	class Decoder(srd.Decoder):
	32	api_version = 3
	33	id = 'maple_bus'
	34	name = 'Maple bus'
	35	longname = 'SEGA Maple bus'
	36	desc = 'Maple bus peripheral protocol for SEGA Dreamcast.'
	37	license = 'gplv2+'
	38	inputs = ['logic']
	39	outputs = ['maple_bus']
	40	channels = (
	41	{'id': 'sdcka', 'name': 'SDCKA', 'desc': 'Data/clock line A'},
	42	{'id': 'sdckb', 'name': 'SDCKB', 'desc': 'Data/clock line B'},
	43	)
	44	annotations = (
	45	('start', 'Start pattern'),
	46	('end', 'End pattern'),
	47	('start-with-crc', 'Start pattern with CRC'),
	48	('occupancy', 'SDCKB occupancy pattern'),
	49	('reset', 'RESET pattern'),
	50	('bit', 'Bit'),
	51	('size', 'Data size'),
	52	('source', 'Source AP'),
	53	('dest', 'Destination AP'),
	54	('command', 'Command'),
	55	('data', 'Data'),
	56	('checksum', 'Checksum'),
	57	('frame-error', 'Frame error'),
	58	('checksum-error', 'Checksum error'),
	59	('size-error', 'Size error'),
	60	)
	61	annotation_rows = (
	62	('bits', 'Bits', (0, 1, 2, 3, 4, 5)),
	63	('fields', 'Fields', (6, 7, 8, 9, 10, 11)),
	64	('warnings', 'Warnings', (12, 13, 14)),
	65	)
	66	binary = (
	67	('size', 'Data size'),
	68	('source', 'Source AP'),
	69	('dest', 'Destination AP'),
	70	('command', 'Command code'),
	71	('data', 'Data'),
	72	('checksum', 'Checksum'),
	73	)
	74
	75	def __init__(self):
	76	pass
	77
	78	def start(self):
	79	self.out_ann = self.register(srd.OUTPUT_ANN)
	80	self.out_binary = self.register(srd.OUTPUT_BINARY)
	81	self.pending_bit_pos = None
	82
	83	def putx(self, data):
	84	self.put(self.ss, self.es, self.out_ann, data)
	85
	86	def putb(self, data):
	87	self.put(self.ss, self.es, self.out_binary, data)
	88
	89	def byte_annotation(self, bintype, d):
	90	return [bintype + 6,
	91	['%s: %02X' % (name, d) for name in ann[bintype]] + ['%02X' % d]]
	92
	93	def got_start(self):
	94	self.putx([0, ['Start pattern', 'Start', 'S']])
	95
	96	def got_end(self):
	97	self.putx([1, ['End pattern', 'End', 'E']])
	98	if self.length != self.expected_length + 1:
	99	self.putx([14, ['Size error', 'L error', 'LE']])
	100
	101	def got_start_with_crc(self):
	102	self.putx([2, ['Start pattern with CRC', 'Start CRC', 'SC']])
	103
	104	def got_occupancy(self):
	105	self.putx([3, ['SDCKB occupancy pattern', 'Occupancy', 'O']])
	106
	107	def got_reset(self):
	108	self.putx([4, ['RESET pattern', 'RESET', 'R']])
	109
	110	def output_pending_bit(self):
	111	if self.pending_bit_pos:
	112	self.put(self.pending_bit_pos, self.pending_bit_pos, self.out_ann, [5, ['Bit: %d' % self.pending_bit, '%d' % self.pending_bit]])
	113
	114	def got_bit(self, n):
	115	self.output_pending_bit()
	116	self.data = self.data * 2 + n
	117	self.pending_bit = n
	118	self.pending_bit_pos = self.samplenum
	119
	120	def got_byte(self):
	121	self.output_pending_bit()
	122	bintype = 4
	123	if self.length < 4:
	124	if self.length == 0:
	125	self.expected_length = 4 * (self.data + 1)
	126	bintype = self.length
	127	elif self.length == self.expected_length:
	128	bintype = 5
	129	if self.data != self.checksum:
	130	self.putx([13, ['Cksum error', 'K error', 'KE']])
	131	self.length = self.length + 1
	132	self.checksum = self.checksum ^ self.data
	133	self.putx(self.byte_annotation(bintype, self.data))
	134	self.putb([bintype, bytes([self.data])])
	135	self.pending_bit_pos = None
	136
	137	def frame_error(self):
	138	self.putx([7, ['Frame error', 'F error', 'FE']])
	139
	140	def handle_start(self):
	141	self.wait({0: 'l', 1: 'h'})
	142	self.ss = self.samplenum
	143	count = 0
	144	while True:
	145	sdcka, sdckb = self.wait([{1: 'f'}, {0: 'r'}])
	146	if self.matched[0]:
	147	count = count + 1
	148	if self.matched[1]:
	149	self.es = self.samplenum
	150	if sdckb == 1:
	151	if count == 4:
	152	self.got_start()
	153	return True
	154	elif count == 6:
	155	self.got_start_with_crc()
	156	return True
	157	elif count == 8:
	158	self.got_occupancy()
	159	return False
	160	elif count >= 14:
	161	self.got_reset()
	162	return False
	163	self.frame_error()
	164	return False
	165
	166	def handle_byte_or_stop(self):
	167	self.ss = self.samplenum
	168	self.pending_bit_pos = None
	169	initial = True
	170	counta = 0
	171	countb = 0
	172	self.data = 0
	173	while countb < 4:
	174	sdcka, sdckb = self.wait([{0: 'f'}, {1: 'f'}])
	175	self.es = self.samplenum
	176	if self.matched[0]:
	177	if counta == countb:
	178	self.got_bit(sdckb)
	179	counta = counta + 1
	180	elif counta == 1 and countb == 0 and self.data == 0 and sdckb == 0:
	181	self.wait([{0: 'h', 1: 'h'}, {0: 'f'}, {1: 'f'}])
	182	self.es = self.samplenum
	183	if self.matched[0]:
	184	self.got_end()
	185	else:
	186	self.frame_error()
	187	return False
	188	else:
	189	self.frame_error()
	190	return False
	191	elif self.matched[1]:
	192	if counta == countb + 1:
	193	self.got_bit(sdcka)
	194	countb = countb + 1
	195	elif counta == 0 and countb == 0 and sdcka == 1 and initial:
	196	self.ss = self.samplenum
	197	initial = False
	198	else:
	199	self.frame_error()
	200	return False
	201	self.wait({0: 'h'})
	202	self.es = self.samplenum
	203	self.got_byte()
	204	return True
	205
	206	def decode(self):
	207	while True:
	208	while not self.handle_start():
	209	pass
	210	self.length = 0
	211	self.expected_length = 4
	212	self.checksum = 0
	213	while self.handle_byte_or_stop():
	214	pass