[libsigrokdecode.git] / decoders / jtag / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

'''
OUTPUT_PYTHON format:

Packet:
[<ptype>, <pdata>]

<ptype>:
 - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
   Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
   'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
   'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
   'EXIT2-IR', 'UPDATE-IR'.
 - 'IR TDI': Bitstring that was clocked into the IR register.
 - 'IR TDO': Bitstring that was clocked out of the IR register.
 - 'DR TDI': Bitstring that was clocked into the DR register.
 - 'DR TDO': Bitstring that was clocked out of the DR register.

All bitstrings are a list consisting of two items. The first is a sequence
of '1' and '0' characters (the right-most character is the LSB. Example:
'01110001', where 1 is the LSB). The second item is a list of ss/es values
for each bit that is in the bitstring.
'''

jtag_states = [
        # Intro "tree"
        'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
        # DR "tree"
        'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
        'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
        # IR "tree"
        'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
        'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
]

class Decoder(srd.Decoder):
    api_version = 3
    id = 'jtag'
    name = 'JTAG'
    longname = 'Joint Test Action Group (IEEE 1149.1)'
    desc = 'Protocol for testing, debugging, and flashing ICs.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['jtag']
    channels = (
        {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
        {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
        {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
        {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
    )
    optional_channels = (
        {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
        {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
        {'id': 'rtck', 'name': 'RTCK',  'desc': 'Return clock signal'},
    )
    annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
        ('bit-tdi', 'Bit (TDI)'),
        ('bit-tdo', 'Bit (TDO)'),
        ('bitstring-tdi', 'Bitstring (TDI)'),
        ('bitstring-tdo', 'Bitstring (TDO)'),
    )
    annotation_rows = (
        ('bits-tdi', 'Bits (TDI)', (16,)),
        ('bits-tdo', 'Bits (TDO)', (17,)),
        ('bitstrings-tdi', 'Bitstring (TDI)', (18,)),
        ('bitstrings-tdo', 'Bitstring (TDO)', (19,)),
        ('states', 'States', tuple(range(15 + 1))),
    )

    def __init__(self):
        # self.state = 'TEST-LOGIC-RESET'
        self.state = 'RUN-TEST/IDLE'
        self.oldstate = None
        self.bits_tdi = []
        self.bits_tdo = []
        self.bits_samplenums_tdi = []
        self.bits_samplenums_tdo = []
        self.ss_item = self.es_item = None
        self.ss_bitstring = self.es_bitstring = None
        self.saved_item = None
        self.first = True
        self.first_bit = True

    def start(self):
        self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss_item, self.es_item, self.out_ann, data)

    def putp(self, data):
        self.put(self.ss_item, self.es_item, self.out_python, data)

    def putx_bs(self, data):
        self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)

    def putp_bs(self, data):
        self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)

    def advance_state_machine(self, tms):
        self.oldstate = self.state

        # Intro "tree"
        if self.state == 'TEST-LOGIC-RESET':
            self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
        elif self.state == 'RUN-TEST/IDLE':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        # DR "tree"
        elif self.state == 'SELECT-DR-SCAN':
            self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
        elif self.state == 'CAPTURE-DR':
            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'SHIFT-DR':
            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'EXIT1-DR':
            self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
        elif self.state == 'PAUSE-DR':
            self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
        elif self.state == 'EXIT2-DR':
            self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'UPDATE-DR':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        # IR "tree"
        elif self.state == 'SELECT-IR-SCAN':
            self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
        elif self.state == 'CAPTURE-IR':
            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'SHIFT-IR':
            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'EXIT1-IR':
            self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
        elif self.state == 'PAUSE-IR':
            self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
        elif self.state == 'EXIT2-IR':
            self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'UPDATE-IR':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

    def handle_rising_tck_edge(self, pins):
        (tdi, tdo, tck, tms, trst, srst, rtck) = pins

        # Rising TCK edges always advance the state machine.
        self.advance_state_machine(tms)

        if self.first:
            # Save the start sample and item for later (no output yet).
            self.ss_item = self.samplenum
            self.first = False
        else:
            # Output the saved item (from the last CLK edge to the current).
            self.es_item = self.samplenum
            # Output the old state (from last rising TCK edge to current one).
            self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
            self.putp(['NEW STATE', self.state])

        # Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values.
        if self.state.startswith('SHIFT-'):
            if self.first_bit:
                self.ss_bitstring = self.samplenum
                self.first_bit = False
            else:
                self.putx([16, [str(self.bits_tdi[0])]])
                self.putx([17, [str(self.bits_tdo[0])]])
                # Use self.samplenum as ES of the previous bit.
                self.bits_samplenums_tdi[0][1] = self.samplenum
                self.bits_samplenums_tdo[0][1] = self.samplenum

            self.bits_tdi.insert(0, tdi)
            self.bits_tdo.insert(0, tdo)

            # Use self.samplenum as SS of the current bit.
            self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
            self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])

        # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
        if self.oldstate.startswith('SHIFT-') and \
           self.state.startswith('EXIT1-'):

            self.es_bitstring = self.samplenum

            t = self.state[-2:] + ' TDI'
            b = ''.join(map(str, self.bits_tdi))
            h = ' (0x%x' % int('0b' + b, 2) + ')'
            s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
            self.putx_bs([18, [s]])
            self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit.
            self.putp_bs([t, [b, self.bits_samplenums_tdi]])
            self.putx([16, [str(self.bits_tdi[0])]]) # Last bit.
            self.bits_tdi = []
            self.bits_samplenums_tdi = []

            t = self.state[-2:] + ' TDO'
            b = ''.join(map(str, self.bits_tdo))
            h = ' (0x%x' % int('0b' + b, 2) + ')'
            s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
            self.putx_bs([19, [s]])
            self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit.
            self.putp_bs([t, [b, self.bits_samplenums_tdo]])
            self.putx([17, [str(self.bits_tdo[0])]]) # Last bit.
            self.bits_tdo = []
            self.bits_samplenums_tdo = []

            self.first_bit = True

            self.ss_bitstring = self.samplenum

        self.ss_item = self.samplenum

    def decode(self):
        while True:
            # Wait for a rising edge on TCK.
            self.handle_rising_tck_edge(self.wait({2: 'r'}))
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22
	23	'''
	24	OUTPUT_PYTHON format:
	25
	26	Packet:
	27	[<ptype>, <pdata>]
	28
	29	<ptype>:
	30	- 'NEW STATE': <pdata> is the new state of the JTAG state machine.
	31	Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
	32	'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
	33	'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
	34	'EXIT2-IR', 'UPDATE-IR'.
	35	- 'IR TDI': Bitstring that was clocked into the IR register.
	36	- 'IR TDO': Bitstring that was clocked out of the IR register.
	37	- 'DR TDI': Bitstring that was clocked into the DR register.
	38	- 'DR TDO': Bitstring that was clocked out of the DR register.
	39
	40	All bitstrings are a list consisting of two items. The first is a sequence
	41	of '1' and '0' characters (the right-most character is the LSB. Example:
	42	'01110001', where 1 is the LSB). The second item is a list of ss/es values
	43	for each bit that is in the bitstring.
	44	'''
	45
	46	jtag_states = [
	47	# Intro "tree"
	48	'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
	49	# DR "tree"
	50	'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
	51	'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
	52	# IR "tree"
	53	'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
	54	'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
	55	]
	56
	57	class Decoder(srd.Decoder):
	58	api_version = 3
	59	id = 'jtag'
	60	name = 'JTAG'
	61	longname = 'Joint Test Action Group (IEEE 1149.1)'
	62	desc = 'Protocol for testing, debugging, and flashing ICs.'
	63	license = 'gplv2+'
	64	inputs = ['logic']
	65	outputs = ['jtag']
	66	channels = (
	67	{'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
	68	{'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
	69	{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
	70	{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
	71	)
	72	optional_channels = (
	73	{'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
	74	{'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
	75	{'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
	76	)
	77	annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
	78	('bit-tdi', 'Bit (TDI)'),
	79	('bit-tdo', 'Bit (TDO)'),
	80	('bitstring-tdi', 'Bitstring (TDI)'),
	81	('bitstring-tdo', 'Bitstring (TDO)'),
	82	)
	83	annotation_rows = (
	84	('bits-tdi', 'Bits (TDI)', (16,)),
	85	('bits-tdo', 'Bits (TDO)', (17,)),
	86	('bitstrings-tdi', 'Bitstring (TDI)', (18,)),
	87	('bitstrings-tdo', 'Bitstring (TDO)', (19,)),
	88	('states', 'States', tuple(range(15 + 1))),
	89	)
	90
	91	def __init__(self):
	92	# self.state = 'TEST-LOGIC-RESET'
	93	self.state = 'RUN-TEST/IDLE'
	94	self.oldstate = None
	95	self.bits_tdi = []
	96	self.bits_tdo = []
	97	self.bits_samplenums_tdi = []
	98	self.bits_samplenums_tdo = []
	99	self.ss_item = self.es_item = None
	100	self.ss_bitstring = self.es_bitstring = None
	101	self.saved_item = None
	102	self.first = True
	103	self.first_bit = True
	104
	105	def start(self):
	106	self.out_python = self.register(srd.OUTPUT_PYTHON)
	107	self.out_ann = self.register(srd.OUTPUT_ANN)
	108
	109	def putx(self, data):
	110	self.put(self.ss_item, self.es_item, self.out_ann, data)
	111
	112	def putp(self, data):
	113	self.put(self.ss_item, self.es_item, self.out_python, data)
	114
	115	def putx_bs(self, data):
	116	self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
	117
	118	def putp_bs(self, data):
	119	self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
	120
	121	def advance_state_machine(self, tms):
	122	self.oldstate = self.state
	123
	124	# Intro "tree"
	125	if self.state == 'TEST-LOGIC-RESET':
	126	self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
	127	elif self.state == 'RUN-TEST/IDLE':
	128	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
	129
	130	# DR "tree"
	131	elif self.state == 'SELECT-DR-SCAN':
	132	self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
	133	elif self.state == 'CAPTURE-DR':
	134	self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
	135	elif self.state == 'SHIFT-DR':
	136	self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
	137	elif self.state == 'EXIT1-DR':
	138	self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
	139	elif self.state == 'PAUSE-DR':
	140	self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
	141	elif self.state == 'EXIT2-DR':
	142	self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
	143	elif self.state == 'UPDATE-DR':
	144	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
	145
	146	# IR "tree"
	147	elif self.state == 'SELECT-IR-SCAN':
	148	self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
	149	elif self.state == 'CAPTURE-IR':
	150	self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
	151	elif self.state == 'SHIFT-IR':
	152	self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
	153	elif self.state == 'EXIT1-IR':
	154	self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
	155	elif self.state == 'PAUSE-IR':
	156	self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
	157	elif self.state == 'EXIT2-IR':
	158	self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
	159	elif self.state == 'UPDATE-IR':
	160	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
	161
	162	def handle_rising_tck_edge(self, pins):
	163	(tdi, tdo, tck, tms, trst, srst, rtck) = pins
	164
	165	# Rising TCK edges always advance the state machine.
	166	self.advance_state_machine(tms)
	167
	168	if self.first:
	169	# Save the start sample and item for later (no output yet).
	170	self.ss_item = self.samplenum
	171	self.first = False
	172	else:
	173	# Output the saved item (from the last CLK edge to the current).
	174	self.es_item = self.samplenum
	175	# Output the old state (from last rising TCK edge to current one).
	176	self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
	177	self.putp(['NEW STATE', self.state])
	178
	179	# Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values.
	180	if self.state.startswith('SHIFT-'):
	181	if self.first_bit:
	182	self.ss_bitstring = self.samplenum
	183	self.first_bit = False
	184	else:
	185	self.putx([16, [str(self.bits_tdi[0])]])
	186	self.putx([17, [str(self.bits_tdo[0])]])
	187	# Use self.samplenum as ES of the previous bit.
	188	self.bits_samplenums_tdi[0][1] = self.samplenum
	189	self.bits_samplenums_tdo[0][1] = self.samplenum
	190
	191	self.bits_tdi.insert(0, tdi)
	192	self.bits_tdo.insert(0, tdo)
	193
	194	# Use self.samplenum as SS of the current bit.
	195	self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
	196	self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
	197
	198	# Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
	199	if self.oldstate.startswith('SHIFT-') and \
	200	self.state.startswith('EXIT1-'):
	201
	202	self.es_bitstring = self.samplenum
	203
	204	t = self.state[-2:] + ' TDI'
	205	b = ''.join(map(str, self.bits_tdi))
	206	h = ' (0x%x' % int('0b' + b, 2) + ')'
	207	s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
	208	self.putx_bs([18, [s]])
	209	self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit.
	210	self.putp_bs([t, [b, self.bits_samplenums_tdi]])
	211	self.putx([16, [str(self.bits_tdi[0])]]) # Last bit.
	212	self.bits_tdi = []
	213	self.bits_samplenums_tdi = []
	214
	215	t = self.state[-2:] + ' TDO'
	216	b = ''.join(map(str, self.bits_tdo))
	217	h = ' (0x%x' % int('0b' + b, 2) + ')'
	218	s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
	219	self.putx_bs([19, [s]])
	220	self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit.
	221	self.putp_bs([t, [b, self.bits_samplenums_tdo]])
	222	self.putx([17, [str(self.bits_tdo[0])]]) # Last bit.
	223	self.bits_tdo = []
	224	self.bits_samplenums_tdo = []
	225
	226	self.first_bit = True
	227
	228	self.ss_bitstring = self.samplenum
	229
	230	self.ss_item = self.samplenum
	231
	232	def decode(self):
	233	while True:
	234	# Wait for a rising edge on TCK.
	235	self.handle_rising_tck_edge(self.wait({2: 'r'}))