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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | ||
22 | ''' | |
23 | OUTPUT_PYTHON format: | |
24 | ||
25 | Packet: | |
26 | [<ptype>, <pdata>] | |
27 | ||
28 | <ptype>: | |
29 | - 'NEW STATE': <pdata> is the new state of the JTAG state machine. | |
30 | Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN', | |
31 | 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR', | |
32 | 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR', | |
33 | 'EXIT2-IR', 'UPDATE-IR'. | |
34 | - 'IR TDI': Bitstring that was clocked into the IR register. | |
35 | - 'IR TDO': Bitstring that was clocked out of the IR register. | |
36 | - 'DR TDI': Bitstring that was clocked into the DR register. | |
37 | - 'DR TDO': Bitstring that was clocked out of the DR register. | |
38 | ||
39 | All bitstrings are a list consisting of two items. The first is a sequence | |
40 | of '1' and '0' characters (the right-most character is the LSB. Example: | |
41 | '01110001', where 1 is the LSB). The second item is a list of ss/es values | |
42 | for each bit that is in the bitstring. | |
43 | ''' | |
44 | ||
45 | jtag_states = [ | |
46 | # Intro "tree" | |
47 | 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', | |
48 | # DR "tree" | |
49 | 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR', | |
50 | 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR', | |
51 | # IR "tree" | |
52 | 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR', | |
53 | 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR', | |
54 | ] | |
55 | ||
56 | class Decoder(srd.Decoder): | |
57 | api_version = 3 | |
58 | id = 'jtag' | |
59 | name = 'JTAG' | |
60 | longname = 'Joint Test Action Group (IEEE 1149.1)' | |
61 | desc = 'Protocol for testing, debugging, and flashing ICs.' | |
62 | license = 'gplv2+' | |
63 | inputs = ['logic'] | |
64 | outputs = ['jtag'] | |
65 | channels = ( | |
66 | {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'}, | |
67 | {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'}, | |
68 | {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'}, | |
69 | {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'}, | |
70 | ) | |
71 | optional_channels = ( | |
72 | {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'}, | |
73 | {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, | |
74 | {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, | |
75 | ) | |
76 | annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \ | |
77 | ('bit-tdi', 'Bit (TDI)'), | |
78 | ('bit-tdo', 'Bit (TDO)'), | |
79 | ('bitstring-tdi', 'Bitstring (TDI)'), | |
80 | ('bitstring-tdo', 'Bitstring (TDO)'), | |
81 | ) | |
82 | annotation_rows = ( | |
83 | ('bits-tdi', 'Bits (TDI)', (16,)), | |
84 | ('bits-tdo', 'Bits (TDO)', (17,)), | |
85 | ('bitstrings-tdi', 'Bitstring (TDI)', (18,)), | |
86 | ('bitstrings-tdo', 'Bitstring (TDO)', (19,)), | |
87 | ('states', 'States', tuple(range(15 + 1))), | |
88 | ) | |
89 | ||
90 | def __init__(self): | |
91 | self.reset() | |
92 | ||
93 | def reset(self): | |
94 | # self.state = 'TEST-LOGIC-RESET' | |
95 | self.state = 'RUN-TEST/IDLE' | |
96 | self.oldstate = None | |
97 | self.bits_tdi = [] | |
98 | self.bits_tdo = [] | |
99 | self.bits_samplenums_tdi = [] | |
100 | self.bits_samplenums_tdo = [] | |
101 | self.ss_item = self.es_item = None | |
102 | self.ss_bitstring = self.es_bitstring = None | |
103 | self.saved_item = None | |
104 | self.first = True | |
105 | self.first_bit = True | |
106 | ||
107 | def start(self): | |
108 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
109 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
110 | ||
111 | def putx(self, data): | |
112 | self.put(self.ss_item, self.es_item, self.out_ann, data) | |
113 | ||
114 | def putp(self, data): | |
115 | self.put(self.ss_item, self.es_item, self.out_python, data) | |
116 | ||
117 | def putx_bs(self, data): | |
118 | self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data) | |
119 | ||
120 | def putp_bs(self, data): | |
121 | self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data) | |
122 | ||
123 | def advance_state_machine(self, tms): | |
124 | self.oldstate = self.state | |
125 | ||
126 | # Intro "tree" | |
127 | if self.state == 'TEST-LOGIC-RESET': | |
128 | self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE' | |
129 | elif self.state == 'RUN-TEST/IDLE': | |
130 | self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' | |
131 | ||
132 | # DR "tree" | |
133 | elif self.state == 'SELECT-DR-SCAN': | |
134 | self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR' | |
135 | elif self.state == 'CAPTURE-DR': | |
136 | self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR' | |
137 | elif self.state == 'SHIFT-DR': | |
138 | self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR' | |
139 | elif self.state == 'EXIT1-DR': | |
140 | self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR' | |
141 | elif self.state == 'PAUSE-DR': | |
142 | self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR' | |
143 | elif self.state == 'EXIT2-DR': | |
144 | self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR' | |
145 | elif self.state == 'UPDATE-DR': | |
146 | self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' | |
147 | ||
148 | # IR "tree" | |
149 | elif self.state == 'SELECT-IR-SCAN': | |
150 | self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR' | |
151 | elif self.state == 'CAPTURE-IR': | |
152 | self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR' | |
153 | elif self.state == 'SHIFT-IR': | |
154 | self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR' | |
155 | elif self.state == 'EXIT1-IR': | |
156 | self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR' | |
157 | elif self.state == 'PAUSE-IR': | |
158 | self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR' | |
159 | elif self.state == 'EXIT2-IR': | |
160 | self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR' | |
161 | elif self.state == 'UPDATE-IR': | |
162 | self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' | |
163 | ||
164 | def handle_rising_tck_edge(self, pins): | |
165 | (tdi, tdo, tck, tms, trst, srst, rtck) = pins | |
166 | ||
167 | # Rising TCK edges always advance the state machine. | |
168 | self.advance_state_machine(tms) | |
169 | ||
170 | if self.first: | |
171 | # Save the start sample and item for later (no output yet). | |
172 | self.ss_item = self.samplenum | |
173 | self.first = False | |
174 | else: | |
175 | # Output the saved item (from the last CLK edge to the current). | |
176 | self.es_item = self.samplenum | |
177 | # Output the old state (from last rising TCK edge to current one). | |
178 | self.putx([jtag_states.index(self.oldstate), [self.oldstate]]) | |
179 | self.putp(['NEW STATE', self.state]) | |
180 | ||
181 | # Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values. | |
182 | if self.state.startswith('SHIFT-'): | |
183 | if self.first_bit: | |
184 | self.ss_bitstring = self.samplenum | |
185 | self.first_bit = False | |
186 | else: | |
187 | self.putx([16, [str(self.bits_tdi[0])]]) | |
188 | self.putx([17, [str(self.bits_tdo[0])]]) | |
189 | # Use self.samplenum as ES of the previous bit. | |
190 | self.bits_samplenums_tdi[0][1] = self.samplenum | |
191 | self.bits_samplenums_tdo[0][1] = self.samplenum | |
192 | ||
193 | self.bits_tdi.insert(0, tdi) | |
194 | self.bits_tdo.insert(0, tdo) | |
195 | ||
196 | # Use self.samplenum as SS of the current bit. | |
197 | self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) | |
198 | self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) | |
199 | ||
200 | # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*. | |
201 | if self.oldstate.startswith('SHIFT-') and \ | |
202 | self.state.startswith('EXIT1-'): | |
203 | ||
204 | self.es_bitstring = self.samplenum | |
205 | ||
206 | t = self.state[-2:] + ' TDI' | |
207 | b = ''.join(map(str, self.bits_tdi)) | |
208 | h = ' (0x%x' % int('0b' + b, 2) + ')' | |
209 | s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits' | |
210 | self.putx_bs([18, [s]]) | |
211 | self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit. | |
212 | self.putp_bs([t, [b, self.bits_samplenums_tdi]]) | |
213 | self.putx([16, [str(self.bits_tdi[0])]]) # Last bit. | |
214 | self.bits_tdi = [] | |
215 | self.bits_samplenums_tdi = [] | |
216 | ||
217 | t = self.state[-2:] + ' TDO' | |
218 | b = ''.join(map(str, self.bits_tdo)) | |
219 | h = ' (0x%x' % int('0b' + b, 2) + ')' | |
220 | s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits' | |
221 | self.putx_bs([19, [s]]) | |
222 | self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit. | |
223 | self.putp_bs([t, [b, self.bits_samplenums_tdo]]) | |
224 | self.putx([17, [str(self.bits_tdo[0])]]) # Last bit. | |
225 | self.bits_tdo = [] | |
226 | self.bits_samplenums_tdo = [] | |
227 | ||
228 | self.first_bit = True | |
229 | ||
230 | self.ss_bitstring = self.samplenum | |
231 | ||
232 | self.ss_item = self.samplenum | |
233 | ||
234 | def decode(self): | |
235 | while True: | |
236 | # Wait for a rising edge on TCK. | |
237 | self.handle_rising_tck_edge(self.wait({2: 'r'})) |