[libsigrokdecode.git] / decoders / jtag / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2020 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd
from common.srdhelper import SrdStrEnum

'''
OUTPUT_PYTHON format:

Packet:
[<ptype>, <pdata>]

<ptype>:
 - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
   Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
   'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
   'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
   'EXIT2-IR', 'UPDATE-IR'.
 - 'IR TDI': Bitstring that was clocked into the IR register.
 - 'IR TDO': Bitstring that was clocked out of the IR register.
 - 'DR TDI': Bitstring that was clocked into the DR register.
 - 'DR TDO': Bitstring that was clocked out of the DR register.

All bitstrings are a list consisting of two items. The first is a sequence
of '1' and '0' characters (the right-most character is the LSB. Example:
'01110001', where 1 is the LSB). The second item is a list of ss/es values
for each bit that is in the bitstring.
'''

s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \
     SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \
     SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR'
St = SrdStrEnum.from_str('St', s)

jtag_states = [s.value for s in St]

class Decoder(srd.Decoder):
    api_version = 3
    id = 'jtag'
    name = 'JTAG'
    longname = 'Joint Test Action Group (IEEE 1149.1)'
    desc = 'Protocol for testing, debugging, and flashing ICs.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['jtag']
    tags = ['Debug/trace']
    channels = (
        {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
        {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
        {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
        {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
    )
    optional_channels = (
        {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
        {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
        {'id': 'rtck', 'name': 'RTCK',  'desc': 'Return clock signal'},
    )
    annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
        ('bit-tdi', 'Bit (TDI)'),
        ('bit-tdo', 'Bit (TDO)'),
        ('bitstring-tdi', 'Bitstring (TDI)'),
        ('bitstring-tdo', 'Bitstring (TDO)'),
    )
    annotation_rows = (
        ('bits-tdi', 'Bits (TDI)', (16,)),
        ('bits-tdo', 'Bits (TDO)', (17,)),
        ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)),
        ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)),
        ('states', 'States', tuple(range(15 + 1))),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        # self.state = St.TEST_LOGIC_RESET
        self.state = St.RUN_TEST_IDLE
        self.oldstate = None
        self.bits_tdi = []
        self.bits_tdo = []
        self.bits_samplenums_tdi = []
        self.bits_samplenums_tdo = []
        self.ss_item = self.es_item = None
        self.ss_bitstring = self.es_bitstring = None
        self.saved_item = None
        self.first = True
        self.first_bit = True

    def start(self):
        self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss_item, self.es_item, self.out_ann, data)

    def putp(self, data):
        self.put(self.ss_item, self.es_item, self.out_python, data)

    def putx_bs(self, data):
        self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)

    def putp_bs(self, data):
        self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)

    def advance_state_machine(self, tms):
        self.oldstate = self.state

        # Intro "tree"
        if self.state == St.TEST_LOGIC_RESET:
            self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE
        elif self.state == St.RUN_TEST_IDLE:
            self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE

        # DR "tree"
        elif self.state == St.SELECT_DR_SCAN:
            self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR
        elif self.state == St.CAPTURE_DR:
            self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR
        elif self.state == St.SHIFT_DR:
            self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR
        elif self.state == St.EXIT1_DR:
            self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR
        elif self.state == St.PAUSE_DR:
            self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR
        elif self.state == St.EXIT2_DR:
            self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR
        elif self.state == St.UPDATE_DR:
            self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE

        # IR "tree"
        elif self.state == St.SELECT_IR_SCAN:
            self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR
        elif self.state == St.CAPTURE_IR:
            self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR
        elif self.state == St.SHIFT_IR:
            self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR
        elif self.state == St.EXIT1_IR:
            self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR
        elif self.state == St.PAUSE_IR:
            self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR
        elif self.state == St.EXIT2_IR:
            self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR
        elif self.state == St.UPDATE_IR:
            self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE

    def handle_rising_tck_edge(self, pins):
        (tdi, tdo, tck, tms, trst, srst, rtck) = pins

        # Rising TCK edges always advance the state machine.
        self.advance_state_machine(tms)

        if self.first:
            # Save the start sample and item for later (no output yet).
            self.ss_item = self.samplenum
            self.first = False
        else:
            # Output the saved item (from the last CLK edge to the current).
            self.es_item = self.samplenum
            # Output the old state (from last rising TCK edge to current one).
            self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]])
            self.putp(['NEW STATE', self.state.value])

        # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values.
        if self.oldstate.value.startswith('SHIFT-') or \
           self.oldstate.value.startswith('EXIT1-'):
            if self.first_bit:
                self.ss_bitstring = self.samplenum
                self.first_bit = False
            else:
                self.putx([16, [str(self.bits_tdi[-1])]])
                self.putx([17, [str(self.bits_tdo[-1])]])
                # Use self.samplenum as ES of the previous bit.
                self.bits_samplenums_tdi[-1][1] = self.samplenum
                self.bits_samplenums_tdo[-1][1] = self.samplenum

            self.bits_tdi.append(tdi)
            self.bits_tdo.append(tdo)

            # Use self.samplenum as SS of the current bit.
            self.bits_samplenums_tdi.append([self.samplenum, -1])
            self.bits_samplenums_tdo.append([self.samplenum, -1])

        # Output all TDI/TDO bits if we just switched to UPDATE-*.
        if self.state.value.startswith('UPDATE-'):

            self.es_bitstring = self.samplenum

            t = self.state.value[-2:] + ' TDI'
            self.bits_tdi.reverse()
            self.bits_samplenums_tdi.reverse()
            b = ''.join(map(str, self.bits_tdi[1:]))
            h = ' (0x%x' % int('0b0' + b, 2) + ')'
            s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
            self.putx_bs([18, [s]])
            self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]])
            self.bits_tdi = []
            self.bits_samplenums_tdi = []

            t = self.state.value[-2:] + ' TDO'
            self.bits_tdo.reverse()
            self.bits_samplenums_tdo.reverse()
            b = ''.join(map(str, self.bits_tdo[1:]))
            h = ' (0x%x' % int('0b0' + b, 2) + ')'
            s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'
            self.putx_bs([19, [s]])
            self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]])
            self.bits_tdo = []
            self.bits_samplenums_tdo = []

            self.first_bit = True

            self.ss_bitstring = self.samplenum

        self.ss_item = self.samplenum

    def decode(self):
        while True:
            # Wait for a rising edge on TCK.
            self.handle_rising_tck_edge(self.wait({2: 'r'}))
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012-2020 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
	21	from common.srdhelper import SrdStrEnum
	22
	23	'''
	24	OUTPUT_PYTHON format:
	25
	26	Packet:
	27	[<ptype>, <pdata>]
	28
	29	<ptype>:
	30	- 'NEW STATE': <pdata> is the new state of the JTAG state machine.
	31	Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
	32	'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
	33	'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
	34	'EXIT2-IR', 'UPDATE-IR'.
	35	- 'IR TDI': Bitstring that was clocked into the IR register.
	36	- 'IR TDO': Bitstring that was clocked out of the IR register.
	37	- 'DR TDI': Bitstring that was clocked into the DR register.
	38	- 'DR TDO': Bitstring that was clocked out of the DR register.
	39
	40	All bitstrings are a list consisting of two items. The first is a sequence
	41	of '1' and '0' characters (the right-most character is the LSB. Example:
	42	'01110001', where 1 is the LSB). The second item is a list of ss/es values
	43	for each bit that is in the bitstring.
	44	'''
	45
	46	s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \
	47	SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \
	48	SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR'
	49	St = SrdStrEnum.from_str('St', s)
	50
	51	jtag_states = [s.value for s in St]
	52
	53	class Decoder(srd.Decoder):
	54	api_version = 3
	55	id = 'jtag'
	56	name = 'JTAG'
	57	longname = 'Joint Test Action Group (IEEE 1149.1)'
	58	desc = 'Protocol for testing, debugging, and flashing ICs.'
	59	license = 'gplv2+'
	60	inputs = ['logic']
	61	outputs = ['jtag']
	62	tags = ['Debug/trace']
	63	channels = (
	64	{'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
	65	{'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
	66	{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
	67	{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
	68	)
	69	optional_channels = (
	70	{'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
	71	{'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
	72	{'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
	73	)
	74	annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
	75	('bit-tdi', 'Bit (TDI)'),
	76	('bit-tdo', 'Bit (TDO)'),
	77	('bitstring-tdi', 'Bitstring (TDI)'),
	78	('bitstring-tdo', 'Bitstring (TDO)'),
	79	)
	80	annotation_rows = (
	81	('bits-tdi', 'Bits (TDI)', (16,)),
	82	('bits-tdo', 'Bits (TDO)', (17,)),
	83	('bitstrings-tdi', 'Bitstrings (TDI)', (18,)),
	84	('bitstrings-tdo', 'Bitstrings (TDO)', (19,)),
	85	('states', 'States', tuple(range(15 + 1))),
	86	)
	87
	88	def __init__(self):
	89	self.reset()
	90
	91	def reset(self):
	92	# self.state = St.TEST_LOGIC_RESET
	93	self.state = St.RUN_TEST_IDLE
	94	self.oldstate = None
	95	self.bits_tdi = []
	96	self.bits_tdo = []
	97	self.bits_samplenums_tdi = []
	98	self.bits_samplenums_tdo = []
	99	self.ss_item = self.es_item = None
	100	self.ss_bitstring = self.es_bitstring = None
	101	self.saved_item = None
	102	self.first = True
	103	self.first_bit = True
	104
	105	def start(self):
	106	self.out_python = self.register(srd.OUTPUT_PYTHON)
	107	self.out_ann = self.register(srd.OUTPUT_ANN)
	108
	109	def putx(self, data):
	110	self.put(self.ss_item, self.es_item, self.out_ann, data)
	111
	112	def putp(self, data):
	113	self.put(self.ss_item, self.es_item, self.out_python, data)
	114
	115	def putx_bs(self, data):
	116	self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
	117
	118	def putp_bs(self, data):
	119	self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
	120
	121	def advance_state_machine(self, tms):
	122	self.oldstate = self.state
	123
	124	# Intro "tree"
	125	if self.state == St.TEST_LOGIC_RESET:
	126	self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE
	127	elif self.state == St.RUN_TEST_IDLE:
	128	self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE
	129
	130	# DR "tree"
	131	elif self.state == St.SELECT_DR_SCAN:
	132	self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR
	133	elif self.state == St.CAPTURE_DR:
	134	self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR
	135	elif self.state == St.SHIFT_DR:
	136	self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR
	137	elif self.state == St.EXIT1_DR:
	138	self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR
	139	elif self.state == St.PAUSE_DR:
	140	self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR
	141	elif self.state == St.EXIT2_DR:
	142	self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR
	143	elif self.state == St.UPDATE_DR:
	144	self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE
	145
	146	# IR "tree"
	147	elif self.state == St.SELECT_IR_SCAN:
	148	self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR
	149	elif self.state == St.CAPTURE_IR:
	150	self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR
	151	elif self.state == St.SHIFT_IR:
	152	self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR
	153	elif self.state == St.EXIT1_IR:
	154	self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR
	155	elif self.state == St.PAUSE_IR:
	156	self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR
	157	elif self.state == St.EXIT2_IR:
	158	self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR
	159	elif self.state == St.UPDATE_IR:
	160	self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE
	161
	162	def handle_rising_tck_edge(self, pins):
	163	(tdi, tdo, tck, tms, trst, srst, rtck) = pins
	164
	165	# Rising TCK edges always advance the state machine.
	166	self.advance_state_machine(tms)
	167
	168	if self.first:
	169	# Save the start sample and item for later (no output yet).
	170	self.ss_item = self.samplenum
	171	self.first = False
	172	else:
	173	# Output the saved item (from the last CLK edge to the current).
	174	self.es_item = self.samplenum
	175	# Output the old state (from last rising TCK edge to current one).
	176	self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]])
	177	self.putp(['NEW STATE', self.state.value])
	178
	179	# Upon SHIFT-/EXIT1- collect the current TDI/TDO values.
	180	if self.oldstate.value.startswith('SHIFT-') or \
	181	self.oldstate.value.startswith('EXIT1-'):
	182	if self.first_bit:
	183	self.ss_bitstring = self.samplenum
	184	self.first_bit = False
	185	else:
	186	self.putx([16, [str(self.bits_tdi[-1])]])
	187	self.putx([17, [str(self.bits_tdo[-1])]])
	188	# Use self.samplenum as ES of the previous bit.
	189	self.bits_samplenums_tdi[-1][1] = self.samplenum
	190	self.bits_samplenums_tdo[-1][1] = self.samplenum
	191
	192	self.bits_tdi.append(tdi)
	193	self.bits_tdo.append(tdo)
	194
	195	# Use self.samplenum as SS of the current bit.
	196	self.bits_samplenums_tdi.append([self.samplenum, -1])
	197	self.bits_samplenums_tdo.append([self.samplenum, -1])
	198
	199	# Output all TDI/TDO bits if we just switched to UPDATE-*.
	200	if self.state.value.startswith('UPDATE-'):
	201
	202	self.es_bitstring = self.samplenum
	203
	204	t = self.state.value[-2:] + ' TDI'
	205	self.bits_tdi.reverse()
	206	self.bits_samplenums_tdi.reverse()
	207	b = ''.join(map(str, self.bits_tdi[1:]))
	208	h = ' (0x%x' % int('0b0' + b, 2) + ')'
	209	s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
	210	self.putx_bs([18, [s]])
	211	self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]])
	212	self.bits_tdi = []
	213	self.bits_samplenums_tdi = []
	214
	215	t = self.state.value[-2:] + ' TDO'
	216	self.bits_tdo.reverse()
	217	self.bits_samplenums_tdo.reverse()
	218	b = ''.join(map(str, self.bits_tdo[1:]))
	219	h = ' (0x%x' % int('0b0' + b, 2) + ')'
	220	s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'
	221	self.putx_bs([19, [s]])
	222	self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]])
	223	self.bits_tdo = []
	224	self.bits_samplenums_tdo = []
	225
	226	self.first_bit = True
	227
	228	self.ss_bitstring = self.samplenum
	229
	230	self.ss_item = self.samplenum
	231
	232	def decode(self):
	233	while True:
	234	# Wait for a rising edge on TCK.
	235	self.handle_rising_tck_edge(self.wait({2: 'r'}))