[libsigrokdecode.git] / decoders / jitter / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd

# Helper dictionary for edge detection.
edge_detector = {
    'rising':  lambda x, y: bool(not x and y),
    'falling': lambda x, y: bool(x and not y),
    'both':    lambda x, y: bool(x ^ y),
}

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 3
    id = 'jitter'
    name = 'Jitter'
    longname = 'Timing jitter calculation'
    desc = 'Retrieves the timing jitter between two digital signals.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['jitter']
    channels = (
        {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
        {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
    )
    options = (
        {'id': 'clk_polarity', 'desc': 'Clock edge polarity',
            'default': 'rising', 'values': ('rising', 'falling', 'both')},
        {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
            'default': 'rising', 'values': ('rising', 'falling', 'both')},
    )
    annotations = (
        ('jitter', 'Jitter value'),
        ('clk_missed', 'Clock missed'),
        ('sig_missed', 'Signal missed'),
    )
    annotation_rows = (
        ('jitter', 'Jitter values', (0,)),
        ('clk_missed', 'Clock missed', (1,)),
        ('sig_missed', 'Signal missed', (2,)),
    )
    binary = (
        ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.state = 'CLK'
        self.samplerate = None
        self.oldclk, self.oldsig = 0, 0
        self.clk_start = None
        self.sig_start = None
        self.clk_missed = 0
        self.sig_missed = 0

    def start(self):
        self.clk_edge = edge_detector[self.options['clk_polarity']]
        self.sig_edge = edge_detector[self.options['sig_polarity']]
        self.out_ann = self.register(srd.OUTPUT_ANN)
        self.out_binary = self.register(srd.OUTPUT_BINARY)
        self.out_clk_missed = self.register(srd.OUTPUT_META,
            meta=(int, 'Clock missed', 'Clock transition missed'))
        self.out_sig_missed = self.register(srd.OUTPUT_META,
            meta=(int, 'Signal missed', 'Resulting signal transition missed'))

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value

    # Helper function for jitter time annotations.
    def putx(self, delta):
        # Adjust granularity.
        if delta == 0 or delta >= 1:
            delta_s = '%.1fs' % (delta)
        elif delta <= 1e-12:
            delta_s = '%.1ffs' % (delta * 1e15)
        elif delta <= 1e-9:
            delta_s = '%.1fps' % (delta * 1e12)
        elif delta <= 1e-6:
            delta_s = '%.1fns' % (delta * 1e9)
        elif delta <= 1e-3:
            delta_s = '%.1fμs' % (delta * 1e6)
        else:
            delta_s = '%.1fms' % (delta * 1e3)

        self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])

    # Helper function for ASCII float jitter values (one value per line).
    def putb(self, delta):
        if delta is None:
            return
        # Format the delta to an ASCII float value terminated by a newline.
        x = str(delta) + '\n'
        self.put(self.clk_start, self.sig_start, self.out_binary,
                 [0, x.encode('UTF-8')])

    # Helper function for missed clock and signal annotations.
    def putm(self, data):
        self.put(self.samplenum, self.samplenum, self.out_ann, data)

    def handle_clk(self, clk, sig):
        if self.clk_start == self.samplenum:
            # Clock transition already treated.
            # We have done everything we can with this sample.
            return True

        if self.clk_edge(self.oldclk, clk):
            # Clock edge found.
            # We note the sample and move to the next state.
            self.clk_start = self.samplenum
            self.state = 'SIG'
            return False
        else:
            if self.sig_start is not None \
               and self.sig_start != self.samplenum \
               and self.sig_edge(self.oldsig, sig):
                # If any transition in the resulting signal
                # occurs while we are waiting for a clock,
                # we increase the missed signal counter.
                self.sig_missed += 1
                self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
                self.putm([2, ['Missed signal', 'MS']])
            # No clock edge found, we have done everything we
            # can with this sample.
            return True

    def handle_sig(self, clk, sig):
        if self.sig_start == self.samplenum:
            # Signal transition already treated.
            # We have done everything we can with this sample.
            return True

        if self.sig_edge(self.oldsig, sig):
            # Signal edge found.
            # We note the sample, calculate the jitter
            # and move to the next state.
            self.sig_start = self.samplenum
            self.state = 'CLK'
            # Calculate and report the timing jitter.
            delta = (self.sig_start - self.clk_start) / self.samplerate
            self.putx(delta)
            self.putb(delta)
            return False
        else:
            if self.clk_start != self.samplenum \
               and self.clk_edge(self.oldclk, clk):
                # If any transition in the clock signal
                # occurs while we are waiting for a resulting
                # signal, we increase the missed clock counter.
                self.clk_missed += 1
                self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
                self.putm([1, ['Missed clock', 'MC']])
            # No resulting signal edge found, we have done
            # everything we can with this sample.
            return True

    def decode(self):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')
        while True:
            # Wait for a transition on CLK and/or SIG.
            clk, sig = self.wait([{0: 'e'}, {1: 'e'}])

            # State machine:
            # For each sample we can move 2 steps forward in the state machine.
            while True:
                # Clock state has the lead.
                if self.state == 'CLK':
                    if self.handle_clk(clk, sig):
                        break
                if self.state == 'SIG':
                    if self.handle_sig(clk, sig):
                        break

            # Save current CLK/SIG values for the next round.
            self.oldclk, self.oldsig = clk, sig
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
	21
	22	# Helper dictionary for edge detection.
	23	edge_detector = {
	24	'rising': lambda x, y: bool(not x and y),
	25	'falling': lambda x, y: bool(x and not y),
	26	'both': lambda x, y: bool(x ^ y),
	27	}
	28
	29	class SamplerateError(Exception):
	30	pass
	31
	32	class Decoder(srd.Decoder):
	33	api_version = 3
	34	id = 'jitter'
	35	name = 'Jitter'
	36	longname = 'Timing jitter calculation'
	37	desc = 'Retrieves the timing jitter between two digital signals.'
	38	license = 'gplv2+'
	39	inputs = ['logic']
	40	outputs = ['jitter']
	41	channels = (
	42	{'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
	43	{'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
	44	)
	45	options = (
	46	{'id': 'clk_polarity', 'desc': 'Clock edge polarity',
	47	'default': 'rising', 'values': ('rising', 'falling', 'both')},
	48	{'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
	49	'default': 'rising', 'values': ('rising', 'falling', 'both')},
	50	)
	51	annotations = (
	52	('jitter', 'Jitter value'),
	53	('clk_missed', 'Clock missed'),
	54	('sig_missed', 'Signal missed'),
	55	)
	56	annotation_rows = (
	57	('jitter', 'Jitter values', (0,)),
	58	('clk_missed', 'Clock missed', (1,)),
	59	('sig_missed', 'Signal missed', (2,)),
	60	)
	61	binary = (
	62	('ascii-float', 'Jitter values as newline-separated ASCII floats'),
	63	)
	64
	65	def __init__(self):
	66	self.reset()
	67
	68	def reset(self):
	69	self.state = 'CLK'
	70	self.samplerate = None
	71	self.oldclk, self.oldsig = 0, 0
	72	self.clk_start = None
	73	self.sig_start = None
	74	self.clk_missed = 0
	75	self.sig_missed = 0
	76
	77	def start(self):
	78	self.clk_edge = edge_detector[self.options['clk_polarity']]
	79	self.sig_edge = edge_detector[self.options['sig_polarity']]
	80	self.out_ann = self.register(srd.OUTPUT_ANN)
	81	self.out_binary = self.register(srd.OUTPUT_BINARY)
	82	self.out_clk_missed = self.register(srd.OUTPUT_META,
	83	meta=(int, 'Clock missed', 'Clock transition missed'))
	84	self.out_sig_missed = self.register(srd.OUTPUT_META,
	85	meta=(int, 'Signal missed', 'Resulting signal transition missed'))
	86
	87	def metadata(self, key, value):
	88	if key == srd.SRD_CONF_SAMPLERATE:
	89	self.samplerate = value
	90
	91	# Helper function for jitter time annotations.
	92	def putx(self, delta):
	93	# Adjust granularity.
	94	if delta == 0 or delta >= 1:
	95	delta_s = '%.1fs' % (delta)
	96	elif delta <= 1e-12:
	97	delta_s = '%.1ffs' % (delta * 1e15)
	98	elif delta <= 1e-9:
	99	delta_s = '%.1fps' % (delta * 1e12)
	100	elif delta <= 1e-6:
	101	delta_s = '%.1fns' % (delta * 1e9)
	102	elif delta <= 1e-3:
	103	delta_s = '%.1fμs' % (delta * 1e6)
	104	else:
	105	delta_s = '%.1fms' % (delta * 1e3)
	106
	107	self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
	108
	109	# Helper function for ASCII float jitter values (one value per line).
	110	def putb(self, delta):
	111	if delta is None:
	112	return
	113	# Format the delta to an ASCII float value terminated by a newline.
	114	x = str(delta) + '\n'
	115	self.put(self.clk_start, self.sig_start, self.out_binary,
	116	[0, x.encode('UTF-8')])
	117
	118	# Helper function for missed clock and signal annotations.
	119	def putm(self, data):
	120	self.put(self.samplenum, self.samplenum, self.out_ann, data)
	121
	122	def handle_clk(self, clk, sig):
	123	if self.clk_start == self.samplenum:
	124	# Clock transition already treated.
	125	# We have done everything we can with this sample.
	126	return True
	127
	128	if self.clk_edge(self.oldclk, clk):
	129	# Clock edge found.
	130	# We note the sample and move to the next state.
	131	self.clk_start = self.samplenum
	132	self.state = 'SIG'
	133	return False
	134	else:
	135	if self.sig_start is not None \
	136	and self.sig_start != self.samplenum \
	137	and self.sig_edge(self.oldsig, sig):
	138	# If any transition in the resulting signal
	139	# occurs while we are waiting for a clock,
	140	# we increase the missed signal counter.
	141	self.sig_missed += 1
	142	self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
	143	self.putm([2, ['Missed signal', 'MS']])
	144	# No clock edge found, we have done everything we
	145	# can with this sample.
	146	return True
	147
	148	def handle_sig(self, clk, sig):
	149	if self.sig_start == self.samplenum:
	150	# Signal transition already treated.
	151	# We have done everything we can with this sample.
	152	return True
	153
	154	if self.sig_edge(self.oldsig, sig):
	155	# Signal edge found.
	156	# We note the sample, calculate the jitter
	157	# and move to the next state.
	158	self.sig_start = self.samplenum
	159	self.state = 'CLK'
	160	# Calculate and report the timing jitter.
	161	delta = (self.sig_start - self.clk_start) / self.samplerate
	162	self.putx(delta)
	163	self.putb(delta)
	164	return False
	165	else:
	166	if self.clk_start != self.samplenum \
	167	and self.clk_edge(self.oldclk, clk):
	168	# If any transition in the clock signal
	169	# occurs while we are waiting for a resulting
	170	# signal, we increase the missed clock counter.
	171	self.clk_missed += 1
	172	self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
	173	self.putm([1, ['Missed clock', 'MC']])
	174	# No resulting signal edge found, we have done
	175	# everything we can with this sample.
	176	return True
	177
	178	def decode(self):
	179	if not self.samplerate:
	180	raise SamplerateError('Cannot decode without samplerate.')
	181	while True:
	182	# Wait for a transition on CLK and/or SIG.
	183	clk, sig = self.wait([{0: 'e'}, {1: 'e'}])
	184
	185	# State machine:
	186	# For each sample we can move 2 steps forward in the state machine.
	187	while True:
	188	# Clock state has the lead.
	189	if self.state == 'CLK':
	190	if self.handle_clk(clk, sig):
	191	break
	192	if self.state == 'SIG':
	193	if self.handle_sig(clk, sig):
	194	break
	195
	196	# Save current CLK/SIG values for the next round.
	197	self.oldclk, self.oldsig = clk, sig