[libsigrokdecode.git] / decoders / i2c / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2010-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# I2C protocol decoder

# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
# TODO: Implement support for 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.

import sigrokdecode as srd

'''
Protocol output format:

I2C packet:
[<cmd>, <data>]

<cmd> is one of:
 - 'START' (START condition)
 - 'START REPEAT' (Repeated START condition)
 - 'ADDRESS READ' (Slave address, read)
 - 'ADDRESS WRITE' (Slave address, write)
 - 'DATA READ' (Data, read)
 - 'DATA WRITE' (Data, write)
 - 'STOP' (STOP condition)
 - 'ACK' (ACK bit)
 - 'NACK' (NACK bit)

<data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
For example, a slave address field could be 0x51 (instead of 0xa2).
For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None.
'''

# CMD: [annotation-type-index, long annotation, short annotation]
proto = {
    'START':           [0, 'Start',         'S'],
    'START REPEAT':    [1, 'Start repeat',  'Sr'],
    'STOP':            [2, 'Stop',          'P'],
    'ACK':             [3, 'ACK',           'A'],
    'NACK':            [4, 'NACK',          'N'],
    'ADDRESS READ':    [5, 'Address read',  'AR'],
    'ADDRESS WRITE':   [6, 'Address write', 'AW'],
    'DATA READ':       [7, 'Data read',     'DR'],
    'DATA WRITE':      [8, 'Data write',    'DW'],
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'i2c'
    name = 'I2C'
    longname = 'Inter-Integrated Circuit'
    desc = 'Two-wire, multi-master, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['i2c']
    probes = [
        {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
        {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
    ]
    optional_probes = []
    options = {
        'address_format': ['Displayed slave address format', 'shifted'],
    }
    annotations = [
        ['Start', 'Start condition'],
        ['Repeat start', 'Repeat start condition'],
        ['Stop', 'Stop condition'],
        ['ACK', 'ACK'],
        ['NACK', 'NACK'],
        ['Address read', 'Address read'],
        ['Address write', 'Address write'],
        ['Data read', 'Data read'],
        ['Data write', 'Data write'],
        ['Warnings', 'Human-readable warnings'],
    ]

    def __init__(self, **kwargs):
        self.startsample = -1
        self.samplenum = None
        self.bitcount = 0
        self.databyte = 0
        self.wr = -1
        self.is_repeat_start = 0
        self.state = 'FIND START'
        self.oldscl = 1
        self.oldsda = 1
        self.oldpins = [1, 1]

    def start(self):
        self.out_proto = self.add(srd.OUTPUT_PYTHON, 'i2c')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')

    def report(self):
        pass

    def putx(self, data):
        self.put(self.startsample, self.samplenum, self.out_ann, data)

    def putp(self, data):
        self.put(self.startsample, self.samplenum, self.out_proto, data)

    def is_start_condition(self, scl, sda):
        # START condition (S): SDA = falling, SCL = high
        if (self.oldsda == 1 and sda == 0) and scl == 1:
            return True
        return False

    def is_data_bit(self, scl, sda):
        # Data sampling of receiver: SCL = rising
        if self.oldscl == 0 and scl == 1:
            return True
        return False

    def is_stop_condition(self, scl, sda):
        # STOP condition (P): SDA = rising, SCL = high
        if (self.oldsda == 0 and sda == 1) and scl == 1:
            return True
        return False

    def found_start(self, scl, sda):
        self.startsample = self.samplenum
        cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
        self.putp([cmd, None])
        self.putx([proto[cmd][0], proto[cmd][1:]])
        self.state = 'FIND ADDRESS'
        self.bitcount = self.databyte = 0
        self.is_repeat_start = 1
        self.wr = -1

    # Gather 8 bits of data plus the ACK/NACK bit.
    def found_address_or_data(self, scl, sda):
        # Address and data are transmitted MSB-first.
        self.databyte <<= 1
        self.databyte |= sda

        if self.bitcount == 0:
            self.startsample = self.samplenum

        # Return if we haven't collected all 8 + 1 bits, yet.
        self.bitcount += 1
        if self.bitcount != 8:
            return

        # We triggered on the ACK/NACK bit, but won't report that until later.
        self.startsample -= 1

        d = self.databyte
        if self.state == 'FIND ADDRESS':
            # The READ/WRITE bit is only in address bytes, not data bytes.
            self.wr = 0 if (self.databyte & 1) else 1
            if self.options['address_format'] == 'shifted':
                d = d >> 1

        if self.state == 'FIND ADDRESS' and self.wr == 1:
            cmd = 'ADDRESS WRITE'
        elif self.state == 'FIND ADDRESS' and self.wr == 0:
            cmd = 'ADDRESS READ'
        elif self.state == 'FIND DATA' and self.wr == 1:
            cmd = 'DATA WRITE'
        elif self.state == 'FIND DATA' and self.wr == 0:
            cmd = 'DATA READ'

        self.putp([cmd, d])
        self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
                  '%s: %02X' % (proto[cmd][2], d), '%02X' % d]])

        # Done with this packet.
        self.startsample = -1
        self.bitcount = self.databyte = 0
        self.state = 'FIND ACK'

    def get_ack(self, scl, sda):
        self.startsample = self.samplenum
        cmd = 'NACK' if (sda == 1) else 'ACK'
        self.putp([cmd, None])
        self.putx([proto[cmd][0], proto[cmd][1:]])
        # There could be multiple data bytes in a row, so either find
        # another data byte or a STOP condition next.
        self.state = 'FIND DATA'

    def found_stop(self, scl, sda):
        self.startsample = self.samplenum
        cmd = 'STOP'
        self.putp([cmd, None])
        self.putx([proto[cmd][0], proto[cmd][1:]])
        self.state = 'FIND START'
        self.is_repeat_start = 0
        self.wr = -1

    def decode(self, ss, es, data):
        for (self.samplenum, pins) in data:

            # Ignore identical samples early on (for performance reasons).
            if self.oldpins == pins:
                continue
            self.oldpins, (scl, sda) = pins, pins

            # TODO: Wait until the bus is idle (SDA = SCL = 1) first?

            # State machine.
            if self.state == 'FIND START':
                if self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
            elif self.state == 'FIND ADDRESS':
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
            elif self.state == 'FIND DATA':
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
                elif self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
                elif self.is_stop_condition(scl, sda):
                    self.found_stop(scl, sda)
            elif self.state == 'FIND ACK':
                if self.is_data_bit(scl, sda):
                    self.get_ack(scl, sda)
            else:
                raise Exception('Invalid state: %s' % self.state)

            # Save current SDA/SCL values for the next round.
            self.oldscl = scl
            self.oldsda = sda
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2010-2013 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# I2C protocol decoder
	22
	23	# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
	24	# TODO: Implement support for 10bit slave addresses.
	25	# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
	26	# TODO: Implement support for detecting various bus errors.
	27
	28	import sigrokdecode as srd
	29
	30	'''
	31	Protocol output format:
	32
	33	I2C packet:
	34	[<cmd>, <data>]
	35
	36	<cmd> is one of:
	37	- 'START' (START condition)
	38	- 'START REPEAT' (Repeated START condition)
	39	- 'ADDRESS READ' (Slave address, read)
	40	- 'ADDRESS WRITE' (Slave address, write)
	41	- 'DATA READ' (Data, read)
	42	- 'DATA WRITE' (Data, write)
	43	- 'STOP' (STOP condition)
	44	- 'ACK' (ACK bit)
	45	- 'NACK' (NACK bit)
	46
	47	<data> is the data or address byte associated with the 'ADDRESS' and 'DATA'
	48	command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
	49	For example, a slave address field could be 0x51 (instead of 0xa2).
	50	For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None.
	51	'''
	52
	53	# CMD: [annotation-type-index, long annotation, short annotation]
	54	proto = {
	55	'START': [0, 'Start', 'S'],
	56	'START REPEAT': [1, 'Start repeat', 'Sr'],
	57	'STOP': [2, 'Stop', 'P'],
	58	'ACK': [3, 'ACK', 'A'],
	59	'NACK': [4, 'NACK', 'N'],
	60	'ADDRESS READ': [5, 'Address read', 'AR'],
	61	'ADDRESS WRITE': [6, 'Address write', 'AW'],
	62	'DATA READ': [7, 'Data read', 'DR'],
	63	'DATA WRITE': [8, 'Data write', 'DW'],
	64	}
	65
	66	class Decoder(srd.Decoder):
	67	api_version = 1
	68	id = 'i2c'
	69	name = 'I2C'
	70	longname = 'Inter-Integrated Circuit'
	71	desc = 'Two-wire, multi-master, serial bus.'
	72	license = 'gplv2+'
	73	inputs = ['logic']
	74	outputs = ['i2c']
	75	probes = [
	76	{'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
	77	{'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
	78	]
	79	optional_probes = []
	80	options = {
	81	'address_format': ['Displayed slave address format', 'shifted'],
	82	}
	83	annotations = [
	84	['Start', 'Start condition'],
	85	['Repeat start', 'Repeat start condition'],
	86	['Stop', 'Stop condition'],
	87	['ACK', 'ACK'],
	88	['NACK', 'NACK'],
	89	['Address read', 'Address read'],
	90	['Address write', 'Address write'],
	91	['Data read', 'Data read'],
	92	['Data write', 'Data write'],
	93	['Warnings', 'Human-readable warnings'],
	94	]
	95
	96	def __init__(self, **kwargs):
	97	self.startsample = -1
	98	self.samplenum = None
	99	self.bitcount = 0
	100	self.databyte = 0
	101	self.wr = -1
	102	self.is_repeat_start = 0
	103	self.state = 'FIND START'
	104	self.oldscl = 1
	105	self.oldsda = 1
	106	self.oldpins = [1, 1]
	107
	108	def start(self):
	109	self.out_proto = self.add(srd.OUTPUT_PYTHON, 'i2c')
	110	self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
	111
	112	def report(self):
	113	pass
	114
	115	def putx(self, data):
	116	self.put(self.startsample, self.samplenum, self.out_ann, data)
	117
	118	def putp(self, data):
	119	self.put(self.startsample, self.samplenum, self.out_proto, data)
	120
	121	def is_start_condition(self, scl, sda):
	122	# START condition (S): SDA = falling, SCL = high
	123	if (self.oldsda == 1 and sda == 0) and scl == 1:
	124	return True
	125	return False
	126
	127	def is_data_bit(self, scl, sda):
	128	# Data sampling of receiver: SCL = rising
	129	if self.oldscl == 0 and scl == 1:
	130	return True
	131	return False
	132
	133	def is_stop_condition(self, scl, sda):
	134	# STOP condition (P): SDA = rising, SCL = high
	135	if (self.oldsda == 0 and sda == 1) and scl == 1:
	136	return True
	137	return False
	138
	139	def found_start(self, scl, sda):
	140	self.startsample = self.samplenum
	141	cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
	142	self.putp([cmd, None])
	143	self.putx([proto[cmd][0], proto[cmd][1:]])
	144	self.state = 'FIND ADDRESS'
	145	self.bitcount = self.databyte = 0
	146	self.is_repeat_start = 1
	147	self.wr = -1
	148
	149	# Gather 8 bits of data plus the ACK/NACK bit.
	150	def found_address_or_data(self, scl, sda):
	151	# Address and data are transmitted MSB-first.
	152	self.databyte <<= 1
	153	self.databyte \|= sda
	154
	155	if self.bitcount == 0:
	156	self.startsample = self.samplenum
	157
	158	# Return if we haven't collected all 8 + 1 bits, yet.
	159	self.bitcount += 1
	160	if self.bitcount != 8:
	161	return
	162
	163	# We triggered on the ACK/NACK bit, but won't report that until later.
	164	self.startsample -= 1
	165
	166	d = self.databyte
	167	if self.state == 'FIND ADDRESS':
	168	# The READ/WRITE bit is only in address bytes, not data bytes.
	169	self.wr = 0 if (self.databyte & 1) else 1
	170	if self.options['address_format'] == 'shifted':
	171	d = d >> 1
	172
	173	if self.state == 'FIND ADDRESS' and self.wr == 1:
	174	cmd = 'ADDRESS WRITE'
	175	elif self.state == 'FIND ADDRESS' and self.wr == 0:
	176	cmd = 'ADDRESS READ'
	177	elif self.state == 'FIND DATA' and self.wr == 1:
	178	cmd = 'DATA WRITE'
	179	elif self.state == 'FIND DATA' and self.wr == 0:
	180	cmd = 'DATA READ'
	181
	182	self.putp([cmd, d])
	183	self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
	184	'%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
	185
	186	# Done with this packet.
	187	self.startsample = -1
	188	self.bitcount = self.databyte = 0
	189	self.state = 'FIND ACK'
	190
	191	def get_ack(self, scl, sda):
	192	self.startsample = self.samplenum
	193	cmd = 'NACK' if (sda == 1) else 'ACK'
	194	self.putp([cmd, None])
	195	self.putx([proto[cmd][0], proto[cmd][1:]])
	196	# There could be multiple data bytes in a row, so either find
	197	# another data byte or a STOP condition next.
	198	self.state = 'FIND DATA'
	199
	200	def found_stop(self, scl, sda):
	201	self.startsample = self.samplenum
	202	cmd = 'STOP'
	203	self.putp([cmd, None])
	204	self.putx([proto[cmd][0], proto[cmd][1:]])
	205	self.state = 'FIND START'
	206	self.is_repeat_start = 0
	207	self.wr = -1
	208
	209	def decode(self, ss, es, data):
	210	for (self.samplenum, pins) in data:
	211
	212	# Ignore identical samples early on (for performance reasons).
	213	if self.oldpins == pins:
	214	continue
	215	self.oldpins, (scl, sda) = pins, pins
	216
	217	# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
	218
	219	# State machine.
	220	if self.state == 'FIND START':
	221	if self.is_start_condition(scl, sda):
	222	self.found_start(scl, sda)
	223	elif self.state == 'FIND ADDRESS':
	224	if self.is_data_bit(scl, sda):
	225	self.found_address_or_data(scl, sda)
	226	elif self.state == 'FIND DATA':
	227	if self.is_data_bit(scl, sda):
	228	self.found_address_or_data(scl, sda)
	229	elif self.is_start_condition(scl, sda):
	230	self.found_start(scl, sda)
	231	elif self.is_stop_condition(scl, sda):
	232	self.found_stop(scl, sda)
	233	elif self.state == 'FIND ACK':
	234	if self.is_data_bit(scl, sda):
	235	self.get_ack(scl, sda)
	236	else:
	237	raise Exception('Invalid state: %s' % self.state)
	238
	239	# Save current SDA/SCL values for the next round.
	240	self.oldscl = scl
	241	self.oldsda = sda
	242