[libsigrokdecode.git] / decoders / i2c / i2c.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

#
# I2C protocol decoder
#

#
# The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
# bus using two signals (SCL = serial clock line, SDA = serial data line).
#
# There can be many devices on the same bus. Each device can potentially be
# master or slave (and that can change during runtime). Both slave and master
# can potentially play the transmitter or receiver role (this can also
# change at runtime).
#
# Possible maximum data rates:
#  - Standard mode: 100 kbit/s
#  - Fast mode: 400 kbit/s
#  - Fast-mode Plus: 1 Mbit/s
#  - High-speed mode: 3.4 Mbit/s
#
# START condition (S): SDA = falling, SCL = high
# Repeated START condition (Sr): same as S
# Data bit sampling: SCL = rising
# STOP condition (P): SDA = rising, SCL = high
#
# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
# Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
# that indicates an ACK, if it's high that indicates a NACK.
#
# After the first START condition, a master sends the device address of the
# slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
# After those 7 bits, a data direction bit is sent. If the bit is low that
# indicates a WRITE operation, if it's high that indicates a READ operation.
#
# Later an optional 10bit slave addressing scheme was added.
#
# Documentation:
# http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
# http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
# http://en.wikipedia.org/wiki/I2C
#

# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
# TODO: Handle clock stretching.
# TODO: Handle combined messages / repeated START.
# TODO: Implement support for 7bit and 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.
# TODO: I2C address of slaves.
# TODO: Handle multiple different I2C devices on same bus
#       -> we need to decode multiple protocols at the same time.

'''
Protocol output format:

I2C packet:
[<i2c_command>, <data>, <ack_bit>]

<i2c_command> is one of:
  - 'START' (START condition)
  - 'START REPEAT' (Repeated START)
  - 'ADDRESS READ' (Address, read)
  - 'ADDRESS WRITE' (Address, write)
  - 'DATA READ' (Data, read)
  - 'DATA WRITE' (Data, write)
  - 'STOP' (STOP condition)

<data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
command. For 'START', 'START REPEAT' and 'STOP', this is None.

<ack_bit> is either 'ACK' or 'NACK', but may also be None.
'''

import sigrokdecode as srd

# Annotation feed formats
ANN_SHIFTED       = 0
ANN_SHIFTED_SHORT = 1
ANN_RAW           = 2

# Values are verbose and short annotation, respectively.
protocol = {
    'START':           ['START',         'S'],
    'START REPEAT':    ['START REPEAT',  'Sr'],
    'STOP':            ['STOP',          'P'],
    'ACK':             ['ACK',           'A'],
    'NACK':            ['NACK',          'N'],
    'ADDRESS READ':    ['ADDRESS READ',  'AR'],
    'ADDRESS WRITE':   ['ADDRESS WRITE', 'AW'],
    'DATA READ':       ['DATA READ',     'DR'],
    'DATA WRITE':      ['DATA WRITE',    'DW'],
}

# States
FIND_START = 0
FIND_ADDRESS = 1
FIND_DATA = 2

class Decoder(srd.Decoder):
    api_version = 1
    id = 'i2c'
    name = 'I2C'
    longname = 'Inter-Integrated Circuit'
    desc = 'I2C is a two-wire, multi-master, serial bus.'
    longdesc = '...'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['i2c']
    probes = [
        {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
        {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
    ]
    extra_probes = []
    options = {
        'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
    }
    annotations = [
        # ANN_SHIFTED
        ['7-bit shifted hex',
         'Read/write bit shifted out from the 8-bit I2C slave address'],
        # ANN_SHIFTED_SHORT
        ['7-bit shifted hex (short)',
         'Read/write bit shifted out from the 8-bit I2C slave address'],
        # ANN_RAW
        ['Raw hex', 'Unaltered raw data'],
    ]

    def __init__(self, **kwargs):
        self.startsample = -1
        self.samplenum = None
        self.bitcount = 0
        self.databyte = 0
        self.wr = -1
        self.is_repeat_start = 0
        self.state = FIND_START
        self.oldscl = None
        self.oldsda = None

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')

    def report(self):
        pass

    def is_start_condition(self, scl, sda):
        # START condition (S): SDA = falling, SCL = high
        if (self.oldsda == 1 and sda == 0) and scl == 1:
            return True
        return False

    def is_data_bit(self, scl, sda):
        # Data sampling of receiver: SCL = rising
        if self.oldscl == 0 and scl == 1:
            return True
        return False

    def is_stop_condition(self, scl, sda):
        # STOP condition (P): SDA = rising, SCL = high
        if (self.oldsda == 0 and sda == 1) and scl == 1:
            return True
        return False

    def found_start(self, scl, sda):
        self.startsample = self.samplenum

        cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
        self.put(self.out_proto, [cmd, None, None])
        self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])

        self.state = FIND_ADDRESS
        self.bitcount = self.databyte = 0
        self.is_repeat_start = 1
        self.wr = -1

    # Gather 8 bits of data plus the ACK/NACK bit.
    def found_address_or_data(self, scl, sda):
        # Address and data are transmitted MSB-first.
        self.databyte <<= 1
        self.databyte |= sda

        if self.bitcount == 0:
            self.startsample = self.samplenum

        # Return if we haven't collected all 8 + 1 bits, yet.
        self.bitcount += 1
        if self.bitcount != 9:
            return

        # Send raw output annotation before we start shifting out
        # read/write and ack/nack bits.
        self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])

        # We received 8 address/data bits and the ACK/NACK bit.
        self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.

        if self.state == FIND_ADDRESS:
            # The READ/WRITE bit is only in address bytes, not data bytes.
            self.wr = 0 if (self.databyte & 1) else 1
            d = self.databyte >> 1
        elif self.state == FIND_DATA:
            d = self.databyte
        else:
            # TODO: Error?
            pass

        # Last bit that came in was the ACK/NACK bit (1 = NACK).
        ack_bit = 'NACK' if (sda == 1) else 'ACK'

        if self.state == FIND_ADDRESS and self.wr == 1:
            cmd = 'ADDRESS WRITE'
        elif self.state == FIND_ADDRESS and self.wr == 0:
            cmd = 'ADDRESS READ'
        elif self.state == FIND_DATA and self.wr == 1:
            cmd = 'DATA WRITE'
        elif self.state == FIND_DATA and self.wr == 0:
            cmd = 'DATA READ'

        self.put(self.out_proto, [cmd, d, ack_bit])
        self.put(self.out_ann, [ANN_SHIFTED,
                 [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT,
                 [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]])

        self.bitcount = self.databyte = 0
        self.startsample = -1

        if self.state == FIND_ADDRESS:
            self.state = FIND_DATA
        elif self.state == FIND_DATA:
            # There could be multiple data bytes in a row.
            # So, either find a STOP condition or another data byte next.
            pass

    def found_stop(self, scl, sda):
        self.startsample = self.samplenum

        self.put(self.out_proto, ['STOP', None, None])
        self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])

        self.state = FIND_START
        self.is_repeat_start = 0
        self.wr = -1

    def put(self, output_id, data):
        # Inject sample range into the call up to sigrok.
        super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)

    def decode(self, ss, es, data):
        for samplenum, (scl, sda) in data:
            self.samplenum = samplenum

            # First sample: Save SCL/SDA value.
            if self.oldscl == None:
                self.oldscl = scl
                self.oldsda = sda
                continue

            # TODO: Wait until the bus is idle (SDA = SCL = 1) first?

            # State machine.
            if self.state == FIND_START:
                if self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
            elif self.state == FIND_ADDRESS:
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
            elif self.state == FIND_DATA:
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
                elif self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
                elif self.is_stop_condition(scl, sda):
                    self.found_stop(scl, sda)
            else:
                raise Exception('Invalid state %d' % self.STATE)

            # Save current SDA/SCL values for the next round.
            self.oldscl = scl
            self.oldsda = sda
Commit	Line	Data
	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	#
	22	# I2C protocol decoder
	23	#
	24
	25	#
	26	# The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
	27	# bus using two signals (SCL = serial clock line, SDA = serial data line).
	28	#
	29	# There can be many devices on the same bus. Each device can potentially be
	30	# master or slave (and that can change during runtime). Both slave and master
	31	# can potentially play the transmitter or receiver role (this can also
	32	# change at runtime).
	33	#
	34	# Possible maximum data rates:
	35	# - Standard mode: 100 kbit/s
	36	# - Fast mode: 400 kbit/s
	37	# - Fast-mode Plus: 1 Mbit/s
	38	# - High-speed mode: 3.4 Mbit/s
	39	#
	40	# START condition (S): SDA = falling, SCL = high
	41	# Repeated START condition (Sr): same as S
	42	# Data bit sampling: SCL = rising
	43	# STOP condition (P): SDA = rising, SCL = high
	44	#
	45	# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
	46	# Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
	47	# that indicates an ACK, if it's high that indicates a NACK.
	48	#
	49	# After the first START condition, a master sends the device address of the
	50	# slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
	51	# After those 7 bits, a data direction bit is sent. If the bit is low that
	52	# indicates a WRITE operation, if it's high that indicates a READ operation.
	53	#
	54	# Later an optional 10bit slave addressing scheme was added.
	55	#
	56	# Documentation:
	57	# http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
	58	# http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
	59	# http://en.wikipedia.org/wiki/I2C
	60	#
	61
	62	# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
	63	# TODO: Handle clock stretching.
	64	# TODO: Handle combined messages / repeated START.
	65	# TODO: Implement support for 7bit and 10bit slave addresses.
	66	# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
	67	# TODO: Implement support for detecting various bus errors.
	68	# TODO: I2C address of slaves.
	69	# TODO: Handle multiple different I2C devices on same bus
	70	# -> we need to decode multiple protocols at the same time.
	71
	72	'''
	73	Protocol output format:
	74
	75	I2C packet:
	76	[<i2c_command>, <data>, <ack_bit>]
	77
	78	<i2c_command> is one of:
	79	- 'START' (START condition)
	80	- 'START REPEAT' (Repeated START)
	81	- 'ADDRESS READ' (Address, read)
	82	- 'ADDRESS WRITE' (Address, write)
	83	- 'DATA READ' (Data, read)
	84	- 'DATA WRITE' (Data, write)
	85	- 'STOP' (STOP condition)
	86
	87	<data> is the data or address byte associated with the 'ADDRESS' and 'DATA'
	88	command. For 'START', 'START REPEAT' and 'STOP', this is None.
	89
	90	<ack_bit> is either 'ACK' or 'NACK', but may also be None.
	91	'''
	92
	93	import sigrokdecode as srd
	94
	95	# Annotation feed formats
	96	ANN_SHIFTED = 0
	97	ANN_SHIFTED_SHORT = 1
	98	ANN_RAW = 2
	99
	100	# Values are verbose and short annotation, respectively.
	101	protocol = {
	102	'START': ['START', 'S'],
	103	'START REPEAT': ['START REPEAT', 'Sr'],
	104	'STOP': ['STOP', 'P'],
	105	'ACK': ['ACK', 'A'],
	106	'NACK': ['NACK', 'N'],
	107	'ADDRESS READ': ['ADDRESS READ', 'AR'],
	108	'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'],
	109	'DATA READ': ['DATA READ', 'DR'],
	110	'DATA WRITE': ['DATA WRITE', 'DW'],
	111	}
	112
	113	# States
	114	FIND_START = 0
	115	FIND_ADDRESS = 1
	116	FIND_DATA = 2
	117
	118	class Decoder(srd.Decoder):
	119	api_version = 1
	120	id = 'i2c'
	121	name = 'I2C'
	122	longname = 'Inter-Integrated Circuit'
	123	desc = 'I2C is a two-wire, multi-master, serial bus.'
	124	longdesc = '...'
	125	license = 'gplv2+'
	126	inputs = ['logic']
	127	outputs = ['i2c']
	128	probes = [
	129	{'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
	130	{'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
	131	]
	132	extra_probes = []
	133	options = {
	134	'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
	135	}
	136	annotations = [
	137	# ANN_SHIFTED
	138	['7-bit shifted hex',
	139	'Read/write bit shifted out from the 8-bit I2C slave address'],
	140	# ANN_SHIFTED_SHORT
	141	['7-bit shifted hex (short)',
	142	'Read/write bit shifted out from the 8-bit I2C slave address'],
	143	# ANN_RAW
	144	['Raw hex', 'Unaltered raw data'],
	145	]
	146
	147	def __init__(self, **kwargs):
	148	self.startsample = -1
	149	self.samplenum = None
	150	self.bitcount = 0
	151	self.databyte = 0
	152	self.wr = -1
	153	self.is_repeat_start = 0
	154	self.state = FIND_START
	155	self.oldscl = None
	156	self.oldsda = None
	157
	158	def start(self, metadata):
	159	self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
	160	self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
	161
	162	def report(self):
	163	pass
	164
	165	def is_start_condition(self, scl, sda):
	166	# START condition (S): SDA = falling, SCL = high
	167	if (self.oldsda == 1 and sda == 0) and scl == 1:
	168	return True
	169	return False
	170
	171	def is_data_bit(self, scl, sda):
	172	# Data sampling of receiver: SCL = rising
	173	if self.oldscl == 0 and scl == 1:
	174	return True
	175	return False
	176
	177	def is_stop_condition(self, scl, sda):
	178	# STOP condition (P): SDA = rising, SCL = high
	179	if (self.oldsda == 0 and sda == 1) and scl == 1:
	180	return True
	181	return False
	182
	183	def found_start(self, scl, sda):
	184	self.startsample = self.samplenum
	185
	186	cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
	187	self.put(self.out_proto, [cmd, None, None])
	188	self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
	189	self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
	190
	191	self.state = FIND_ADDRESS
	192	self.bitcount = self.databyte = 0
	193	self.is_repeat_start = 1
	194	self.wr = -1
	195
	196	# Gather 8 bits of data plus the ACK/NACK bit.
	197	def found_address_or_data(self, scl, sda):
	198	# Address and data are transmitted MSB-first.
	199	self.databyte <<= 1
	200	self.databyte \|= sda
	201
	202	if self.bitcount == 0:
	203	self.startsample = self.samplenum
	204
	205	# Return if we haven't collected all 8 + 1 bits, yet.
	206	self.bitcount += 1
	207	if self.bitcount != 9:
	208	return
	209
	210	# Send raw output annotation before we start shifting out
	211	# read/write and ack/nack bits.
	212	self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
	213
	214	# We received 8 address/data bits and the ACK/NACK bit.
	215	self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
	216
	217	if self.state == FIND_ADDRESS:
	218	# The READ/WRITE bit is only in address bytes, not data bytes.
	219	self.wr = 0 if (self.databyte & 1) else 1
	220	d = self.databyte >> 1
	221	elif self.state == FIND_DATA:
	222	d = self.databyte
	223	else:
	224	# TODO: Error?
	225	pass
	226
	227	# Last bit that came in was the ACK/NACK bit (1 = NACK).
	228	ack_bit = 'NACK' if (sda == 1) else 'ACK'
	229
	230	if self.state == FIND_ADDRESS and self.wr == 1:
	231	cmd = 'ADDRESS WRITE'
	232	elif self.state == FIND_ADDRESS and self.wr == 0:
	233	cmd = 'ADDRESS READ'
	234	elif self.state == FIND_DATA and self.wr == 1:
	235	cmd = 'DATA WRITE'
	236	elif self.state == FIND_DATA and self.wr == 0:
	237	cmd = 'DATA READ'
	238
	239	self.put(self.out_proto, [cmd, d, ack_bit])
	240	self.put(self.out_ann, [ANN_SHIFTED,
	241	[protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]])
	242	self.put(self.out_ann, [ANN_SHIFTED_SHORT,
	243	[protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]])
	244
	245	self.bitcount = self.databyte = 0
	246	self.startsample = -1
	247
	248	if self.state == FIND_ADDRESS:
	249	self.state = FIND_DATA
	250	elif self.state == FIND_DATA:
	251	# There could be multiple data bytes in a row.
	252	# So, either find a STOP condition or another data byte next.
	253	pass
	254
	255	def found_stop(self, scl, sda):
	256	self.startsample = self.samplenum
	257
	258	self.put(self.out_proto, ['STOP', None, None])
	259	self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
	260	self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
	261
	262	self.state = FIND_START
	263	self.is_repeat_start = 0
	264	self.wr = -1
	265
	266	def put(self, output_id, data):
	267	# Inject sample range into the call up to sigrok.
	268	super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
	269
	270	def decode(self, ss, es, data):
	271	for samplenum, (scl, sda) in data:
	272	self.samplenum = samplenum
	273
	274	# First sample: Save SCL/SDA value.
	275	if self.oldscl == None:
	276	self.oldscl = scl
	277	self.oldsda = sda
	278	continue
	279
	280	# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
	281
	282	# State machine.
	283	if self.state == FIND_START:
	284	if self.is_start_condition(scl, sda):
	285	self.found_start(scl, sda)
	286	elif self.state == FIND_ADDRESS:
	287	if self.is_data_bit(scl, sda):
	288	self.found_address_or_data(scl, sda)
	289	elif self.state == FIND_DATA:
	290	if self.is_data_bit(scl, sda):
	291	self.found_address_or_data(scl, sda)
	292	elif self.is_start_condition(scl, sda):
	293	self.found_start(scl, sda)
	294	elif self.is_stop_condition(scl, sda):
	295	self.found_stop(scl, sda)
	296	else:
	297	raise Exception('Invalid state %d' % self.STATE)
	298
	299	# Save current SDA/SCL values for the next round.
	300	self.oldscl = scl
	301	self.oldsda = sda
	302