[libsigrokdecode.git] / decoders / i2c / i2c.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# I2C protocol decoder

# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
# TODO: Handle clock stretching.
# TODO: Handle combined messages / repeated START.
# TODO: Implement support for 7bit and 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.
# TODO: I2C address of slaves.
# TODO: Handle multiple different I2C devices on same bus
#       -> we need to decode multiple protocols at the same time.

import sigrokdecode as srd

# Annotation feed formats
ANN_SHIFTED = 0
ANN_SHIFTED_SHORT = 1
ANN_RAW = 2

# Values are verbose and short annotation, respectively.
protocol = {
    'START':           ['START',         'S'],
    'START REPEAT':    ['START REPEAT',  'Sr'],
    'STOP':            ['STOP',          'P'],
    'ACK':             ['ACK',           'A'],
    'NACK':            ['NACK',          'N'],
    'ADDRESS READ':    ['ADDRESS READ',  'AR'],
    'ADDRESS WRITE':   ['ADDRESS WRITE', 'AW'],
    'DATA READ':       ['DATA READ',     'DR'],
    'DATA WRITE':      ['DATA WRITE',    'DW'],
}

# States
FIND_START = 0
FIND_ADDRESS = 1
FIND_DATA = 2
FIND_ACK = 3

class Decoder(srd.Decoder):
    api_version = 1
    id = 'i2c'
    name = 'I2C'
    longname = 'Inter-Integrated Circuit'
    desc = 'I2C is a two-wire, multi-master, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['i2c']
    probes = [
        {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
        {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
    ]
    optional_probes = []
    options = {
        'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
    }
    annotations = [
        # ANN_SHIFTED
        ['7-bit shifted hex',
         'Read/write bit shifted out from the 8-bit I2C slave address'],
        # ANN_SHIFTED_SHORT
        ['7-bit shifted hex (short)',
         'Read/write bit shifted out from the 8-bit I2C slave address'],
        # ANN_RAW
        ['Raw hex', 'Unaltered raw data'],
    ]

    def __init__(self, **kwargs):
        self.startsample = -1
        self.samplenum = None
        self.bitcount = 0
        self.databyte = 0
        self.wr = -1
        self.is_repeat_start = 0
        self.state = FIND_START
        self.oldscl = None
        self.oldsda = None

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')

    def report(self):
        pass

    def is_start_condition(self, scl, sda):
        # START condition (S): SDA = falling, SCL = high
        if (self.oldsda == 1 and sda == 0) and scl == 1:
            return True
        return False

    def is_data_bit(self, scl, sda):
        # Data sampling of receiver: SCL = rising
        if self.oldscl == 0 and scl == 1:
            return True
        return False

    def is_stop_condition(self, scl, sda):
        # STOP condition (P): SDA = rising, SCL = high
        if (self.oldsda == 0 and sda == 1) and scl == 1:
            return True
        return False

    def found_start(self, scl, sda):
        self.startsample = self.samplenum

        cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
        self.put(self.out_proto, [cmd, None])
        self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])

        self.state = FIND_ADDRESS
        self.bitcount = self.databyte = 0
        self.is_repeat_start = 1
        self.wr = -1

    # Gather 8 bits of data plus the ACK/NACK bit.
    def found_address_or_data(self, scl, sda):
        # Address and data are transmitted MSB-first.
        self.databyte <<= 1
        self.databyte |= sda

        if self.bitcount == 0:
            self.startsample = self.samplenum

        # Return if we haven't collected all 8 + 1 bits, yet.
        self.bitcount += 1
        if self.bitcount != 8:
            return

        # We triggered on the ACK/NACK bit, but won't report that until later.
        self.startsample -= 1

        # Send raw output annotation before we start shifting out
        # read/write and ACK/NACK bits.
        self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])

        if self.state == FIND_ADDRESS:
            # The READ/WRITE bit is only in address bytes, not data bytes.
            self.wr = 0 if (self.databyte & 1) else 1
            d = self.databyte >> 1
        elif self.state == FIND_DATA:
            d = self.databyte

        if self.state == FIND_ADDRESS and self.wr == 1:
            cmd = 'ADDRESS WRITE'
        elif self.state == FIND_ADDRESS and self.wr == 0:
            cmd = 'ADDRESS READ'
        elif self.state == FIND_DATA and self.wr == 1:
            cmd = 'DATA WRITE'
        elif self.state == FIND_DATA and self.wr == 0:
            cmd = 'DATA READ'

        self.put(self.out_proto, [cmd, d])
        self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0], '0x%02x' % d]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1], '0x%02x' % d]])

        # Done with this packet.
        self.startsample = -1
        self.bitcount = self.databyte = 0
        self.state = FIND_ACK

    def get_ack(self, scl, sda):
        self.startsample = self.samplenum
        ack_bit = 'NACK' if (sda == 1) else 'ACK'
        self.put(self.out_proto, [ack_bit, None])
        self.put(self.out_ann, [ANN_SHIFTED, [protocol[ack_bit][0]]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[ack_bit][1]]])
        # There could be multiple data bytes in a row, so either find
        # another data byte or a STOP condition next.
        self.state = FIND_DATA

    def found_stop(self, scl, sda):
        self.startsample = self.samplenum
        self.put(self.out_proto, ['STOP', None])
        self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
        self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])

        self.state = FIND_START
        self.is_repeat_start = 0
        self.wr = -1

    def put(self, output_id, data):
        # Inject sample range into the call up to sigrok.
        super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)

    def decode(self, ss, es, data):
        for samplenum, (scl, sda) in data:
            self.samplenum = samplenum

            # First sample: Save SCL/SDA value.
            if self.oldscl == None:
                self.oldscl = scl
                self.oldsda = sda
                continue

            # TODO: Wait until the bus is idle (SDA = SCL = 1) first?

            # State machine.
            if self.state == FIND_START:
                if self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
            elif self.state == FIND_ADDRESS:
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
            elif self.state == FIND_DATA:
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
                elif self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
                elif self.is_stop_condition(scl, sda):
                    self.found_stop(scl, sda)
            elif self.state == FIND_ACK:
                if self.is_data_bit(scl, sda):
                    self.get_ack(scl, sda)
            else:
                raise Exception('Invalid state %d' % self.STATE)

            # Save current SDA/SCL values for the next round.
            self.oldscl = scl
            self.oldsda = sda
Commit	Line	Data
	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# I2C protocol decoder
	22
	23	# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
	24	# TODO: Handle clock stretching.
	25	# TODO: Handle combined messages / repeated START.
	26	# TODO: Implement support for 7bit and 10bit slave addresses.
	27	# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
	28	# TODO: Implement support for detecting various bus errors.
	29	# TODO: I2C address of slaves.
	30	# TODO: Handle multiple different I2C devices on same bus
	31	# -> we need to decode multiple protocols at the same time.
	32
	33	import sigrokdecode as srd
	34
	35	# Annotation feed formats
	36	ANN_SHIFTED = 0
	37	ANN_SHIFTED_SHORT = 1
	38	ANN_RAW = 2
	39
	40	# Values are verbose and short annotation, respectively.
	41	protocol = {
	42	'START': ['START', 'S'],
	43	'START REPEAT': ['START REPEAT', 'Sr'],
	44	'STOP': ['STOP', 'P'],
	45	'ACK': ['ACK', 'A'],
	46	'NACK': ['NACK', 'N'],
	47	'ADDRESS READ': ['ADDRESS READ', 'AR'],
	48	'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'],
	49	'DATA READ': ['DATA READ', 'DR'],
	50	'DATA WRITE': ['DATA WRITE', 'DW'],
	51	}
	52
	53	# States
	54	FIND_START = 0
	55	FIND_ADDRESS = 1
	56	FIND_DATA = 2
	57	FIND_ACK = 3
	58
	59	class Decoder(srd.Decoder):
	60	api_version = 1
	61	id = 'i2c'
	62	name = 'I2C'
	63	longname = 'Inter-Integrated Circuit'
	64	desc = 'I2C is a two-wire, multi-master, serial bus.'
	65	license = 'gplv2+'
	66	inputs = ['logic']
	67	outputs = ['i2c']
	68	probes = [
	69	{'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
	70	{'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
	71	]
	72	optional_probes = []
	73	options = {
	74	'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
	75	}
	76	annotations = [
	77	# ANN_SHIFTED
	78	['7-bit shifted hex',
	79	'Read/write bit shifted out from the 8-bit I2C slave address'],
	80	# ANN_SHIFTED_SHORT
	81	['7-bit shifted hex (short)',
	82	'Read/write bit shifted out from the 8-bit I2C slave address'],
	83	# ANN_RAW
	84	['Raw hex', 'Unaltered raw data'],
	85	]
	86
	87	def __init__(self, **kwargs):
	88	self.startsample = -1
	89	self.samplenum = None
	90	self.bitcount = 0
	91	self.databyte = 0
	92	self.wr = -1
	93	self.is_repeat_start = 0
	94	self.state = FIND_START
	95	self.oldscl = None
	96	self.oldsda = None
	97
	98	def start(self, metadata):
	99	self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
	100	self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
	101
	102	def report(self):
	103	pass
	104
	105	def is_start_condition(self, scl, sda):
	106	# START condition (S): SDA = falling, SCL = high
	107	if (self.oldsda == 1 and sda == 0) and scl == 1:
	108	return True
	109	return False
	110
	111	def is_data_bit(self, scl, sda):
	112	# Data sampling of receiver: SCL = rising
	113	if self.oldscl == 0 and scl == 1:
	114	return True
	115	return False
	116
	117	def is_stop_condition(self, scl, sda):
	118	# STOP condition (P): SDA = rising, SCL = high
	119	if (self.oldsda == 0 and sda == 1) and scl == 1:
	120	return True
	121	return False
	122
	123	def found_start(self, scl, sda):
	124	self.startsample = self.samplenum
	125
	126	cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
	127	self.put(self.out_proto, [cmd, None])
	128	self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
	129	self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
	130
	131	self.state = FIND_ADDRESS
	132	self.bitcount = self.databyte = 0
	133	self.is_repeat_start = 1
	134	self.wr = -1
	135
	136	# Gather 8 bits of data plus the ACK/NACK bit.
	137	def found_address_or_data(self, scl, sda):
	138	# Address and data are transmitted MSB-first.
	139	self.databyte <<= 1
	140	self.databyte \|= sda
	141
	142	if self.bitcount == 0:
	143	self.startsample = self.samplenum
	144
	145	# Return if we haven't collected all 8 + 1 bits, yet.
	146	self.bitcount += 1
	147	if self.bitcount != 8:
	148	return
	149
	150	# We triggered on the ACK/NACK bit, but won't report that until later.
	151	self.startsample -= 1
	152
	153	# Send raw output annotation before we start shifting out
	154	# read/write and ACK/NACK bits.
	155	self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
	156
	157	if self.state == FIND_ADDRESS:
	158	# The READ/WRITE bit is only in address bytes, not data bytes.
	159	self.wr = 0 if (self.databyte & 1) else 1
	160	d = self.databyte >> 1
	161	elif self.state == FIND_DATA:
	162	d = self.databyte
	163
	164	if self.state == FIND_ADDRESS and self.wr == 1:
	165	cmd = 'ADDRESS WRITE'
	166	elif self.state == FIND_ADDRESS and self.wr == 0:
	167	cmd = 'ADDRESS READ'
	168	elif self.state == FIND_DATA and self.wr == 1:
	169	cmd = 'DATA WRITE'
	170	elif self.state == FIND_DATA and self.wr == 0:
	171	cmd = 'DATA READ'
	172
	173	self.put(self.out_proto, [cmd, d])
	174	self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0], '0x%02x' % d]])
	175	self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1], '0x%02x' % d]])
	176
	177	# Done with this packet.
	178	self.startsample = -1
	179	self.bitcount = self.databyte = 0
	180	self.state = FIND_ACK
	181
	182	def get_ack(self, scl, sda):
	183	self.startsample = self.samplenum
	184	ack_bit = 'NACK' if (sda == 1) else 'ACK'
	185	self.put(self.out_proto, [ack_bit, None])
	186	self.put(self.out_ann, [ANN_SHIFTED, [protocol[ack_bit][0]]])
	187	self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[ack_bit][1]]])
	188	# There could be multiple data bytes in a row, so either find
	189	# another data byte or a STOP condition next.
	190	self.state = FIND_DATA
	191
	192	def found_stop(self, scl, sda):
	193	self.startsample = self.samplenum
	194	self.put(self.out_proto, ['STOP', None])
	195	self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
	196	self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
	197
	198	self.state = FIND_START
	199	self.is_repeat_start = 0
	200	self.wr = -1
	201
	202	def put(self, output_id, data):
	203	# Inject sample range into the call up to sigrok.
	204	super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
	205
	206	def decode(self, ss, es, data):
	207	for samplenum, (scl, sda) in data:
	208	self.samplenum = samplenum
	209
	210	# First sample: Save SCL/SDA value.
	211	if self.oldscl == None:
	212	self.oldscl = scl
	213	self.oldsda = sda
	214	continue
	215
	216	# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
	217
	218	# State machine.
	219	if self.state == FIND_START:
	220	if self.is_start_condition(scl, sda):
	221	self.found_start(scl, sda)
	222	elif self.state == FIND_ADDRESS:
	223	if self.is_data_bit(scl, sda):
	224	self.found_address_or_data(scl, sda)
	225	elif self.state == FIND_DATA:
	226	if self.is_data_bit(scl, sda):
	227	self.found_address_or_data(scl, sda)
	228	elif self.is_start_condition(scl, sda):
	229	self.found_start(scl, sda)
	230	elif self.is_stop_condition(scl, sda):
	231	self.found_stop(scl, sda)
	232	elif self.state == FIND_ACK:
	233	if self.is_data_bit(scl, sda):
	234	self.get_ack(scl, sda)
	235	else:
	236	raise Exception('Invalid state %d' % self.STATE)
	237
	238	# Save current SDA/SCL values for the next round.
	239	self.oldscl = scl
	240	self.oldsda = sda
	241