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1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # I2C protocol decoder | |
23 | # | |
24 | ||
25 | # | |
26 | # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master | |
27 | # bus using two signals (SCL = serial clock line, SDA = serial data line). | |
28 | # | |
29 | # There can be many devices on the same bus. Each device can potentially be | |
30 | # master or slave (and that can change during runtime). Both slave and master | |
31 | # can potentially play the transmitter or receiver role (this can also | |
32 | # change at runtime). | |
33 | # | |
34 | # Possible maximum data rates: | |
35 | # - Standard mode: 100 kbit/s | |
36 | # - Fast mode: 400 kbit/s | |
37 | # - Fast-mode Plus: 1 Mbit/s | |
38 | # - High-speed mode: 3.4 Mbit/s | |
39 | # | |
40 | # START condition (S): SDA = falling, SCL = high | |
41 | # Repeated START condition (Sr): same as S | |
42 | # Data bit sampling: SCL = rising | |
43 | # STOP condition (P): SDA = rising, SCL = high | |
44 | # | |
45 | # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first). | |
46 | # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low, | |
47 | # that indicates an ACK, if it's high that indicates a NACK. | |
48 | # | |
49 | # After the first START condition, a master sends the device address of the | |
50 | # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first). | |
51 | # After those 7 bits, a data direction bit is sent. If the bit is low that | |
52 | # indicates a WRITE operation, if it's high that indicates a READ operation. | |
53 | # | |
54 | # Later an optional 10bit slave addressing scheme was added. | |
55 | # | |
56 | # Documentation: | |
57 | # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec) | |
58 | # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec) | |
59 | # http://en.wikipedia.org/wiki/I2C | |
60 | # | |
61 | ||
62 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. | |
63 | # TODO: Handle clock stretching. | |
64 | # TODO: Handle combined messages / repeated START. | |
65 | # TODO: Implement support for 7bit and 10bit slave addresses. | |
66 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). | |
67 | # TODO: Implement support for detecting various bus errors. | |
68 | # TODO: I2C address of slaves. | |
69 | # TODO: Handle multiple different I2C devices on same bus | |
70 | # -> we need to decode multiple protocols at the same time. | |
71 | ||
72 | # | |
73 | # I2C protocol output format: | |
74 | # | |
75 | # The protocol output consists of a (Python) list of I2C "packets", each of | |
76 | # which is of the form | |
77 | # | |
78 | # [<i2c_command>, <data>, <ack_bit>] | |
79 | # | |
80 | # <i2c_command> is one of: | |
81 | # - 'START' (START condition) | |
82 | # - 'START_REPEAT' (Repeated START) | |
83 | # - 'ADDRESS_READ' (Slave address, read) | |
84 | # - 'ADDRESS_WRITE' (Slave address, write) | |
85 | # - 'DATA_READ' (Data, read) | |
86 | # - 'DATA_WRITE' (Data, write) | |
87 | # - 'STOP' (STOP condition) | |
88 | # | |
89 | # <data> is the data or address byte associated with the ADDRESS_* and DATA_* | |
90 | # command. For START, START_REPEAT and STOP, this is None. | |
91 | # | |
92 | # <ack_bit> is either 'ACK' or 'NACK', but may also be None. | |
93 | # | |
94 | ||
95 | import sigrokdecode as srd | |
96 | ||
97 | # Annotation feed formats | |
98 | ANN_SHIFTED = 0 | |
99 | ANN_SHIFTED_SHORT = 1 | |
100 | ANN_RAW = 2 | |
101 | ||
102 | # Values are verbose and short annotation, respectively. | |
103 | protocol = { | |
104 | 'START': ['START', 'S'], | |
105 | 'START_REPEAT': ['START REPEAT', 'Sr'], | |
106 | 'STOP': ['STOP', 'P'], | |
107 | 'ACK': ['ACK', 'A'], | |
108 | 'NACK': ['NACK', 'N'], | |
109 | 'ADDRESS_READ': ['ADDRESS READ', 'AR'], | |
110 | 'ADDRESS_WRITE': ['ADDRESS WRITE', 'AW'], | |
111 | 'DATA_READ': ['DATA READ', 'DR'], | |
112 | 'DATA_WRITE': ['DATA WRITE', 'DW'], | |
113 | } | |
114 | ||
115 | # States | |
116 | FIND_START = 0 | |
117 | FIND_ADDRESS = 1 | |
118 | FIND_DATA = 2 | |
119 | ||
120 | class Decoder(srd.Decoder): | |
121 | id = 'i2c' | |
122 | name = 'I2C' | |
123 | longname = 'Inter-Integrated Circuit' | |
124 | desc = 'I2C is a two-wire, multi-master, serial bus.' | |
125 | longdesc = '...' | |
126 | author = 'Uwe Hermann' | |
127 | email = 'uwe@hermann-uwe.de' | |
128 | license = 'gplv2+' | |
129 | inputs = ['logic'] | |
130 | outputs = ['i2c'] | |
131 | probes = [ | |
132 | {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, | |
133 | {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, | |
134 | ] | |
135 | options = { | |
136 | 'address-space': ['Address space (in bits)', 7], | |
137 | } | |
138 | annotations = [ | |
139 | # ANN_SHIFTED | |
140 | ['7-bit shifted hex', | |
141 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
142 | # ANN_SHIFTED_SHORT | |
143 | ['7-bit shifted hex (short)', | |
144 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
145 | # ANN_RAW | |
146 | ['Raw hex', 'Unaltered raw data'], | |
147 | ] | |
148 | ||
149 | def __init__(self, **kwargs): | |
150 | self.samplecnt = 0 | |
151 | self.bitcount = 0 | |
152 | self.databyte = 0 | |
153 | self.wr = -1 | |
154 | self.startsample = -1 | |
155 | self.is_repeat_start = 0 | |
156 | self.state = FIND_START | |
157 | self.oldscl = None | |
158 | self.oldsda = None | |
159 | ||
160 | def start(self, metadata): | |
161 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c') | |
162 | self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c') | |
163 | ||
164 | def report(self): | |
165 | pass | |
166 | ||
167 | def is_start_condition(self, scl, sda): | |
168 | # START condition (S): SDA = falling, SCL = high | |
169 | if (self.oldsda == 1 and sda == 0) and scl == 1: | |
170 | return True | |
171 | return False | |
172 | ||
173 | def is_data_bit(self, scl, sda): | |
174 | # Data sampling of receiver: SCL = rising | |
175 | if self.oldscl == 0 and scl == 1: | |
176 | return True | |
177 | return False | |
178 | ||
179 | def is_stop_condition(self, scl, sda): | |
180 | # STOP condition (P): SDA = rising, SCL = high | |
181 | if (self.oldsda == 0 and sda == 1) and scl == 1: | |
182 | return True | |
183 | return False | |
184 | ||
185 | def found_start(self, scl, sda): | |
186 | cmd = 'START_REPEAT' if (self.is_repeat_start == 1) else 'START' | |
187 | ||
188 | self.put(self.out_proto, [cmd, None, None]) | |
189 | self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]]) | |
190 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]]) | |
191 | ||
192 | self.state = FIND_ADDRESS | |
193 | self.bitcount = self.databyte = 0 | |
194 | self.is_repeat_start = 1 | |
195 | self.wr = -1 | |
196 | ||
197 | def found_address_or_data(self, scl, sda): | |
198 | # Gather 8 bits of data plus the ACK/NACK bit. | |
199 | ||
200 | if self.startsample == -1: | |
201 | # TODO: Should be samplenum, as received from the feed. | |
202 | self.startsample = self.samplecnt | |
203 | self.bitcount += 1 | |
204 | ||
205 | # Address and data are transmitted MSB-first. | |
206 | self.databyte <<= 1 | |
207 | self.databyte |= sda | |
208 | ||
209 | # Return if we haven't collected all 8 + 1 bits, yet. | |
210 | if self.bitcount != 9: | |
211 | return | |
212 | ||
213 | # Send raw output annotation before we start shifting out | |
214 | # read/write and ack/nack bits. | |
215 | self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]]) | |
216 | ||
217 | # We received 8 address/data bits and the ACK/NACK bit. | |
218 | self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. | |
219 | ||
220 | if self.state == FIND_ADDRESS: | |
221 | # The READ/WRITE bit is only in address bytes, not data bytes. | |
222 | self.wr = 0 if (self.databyte & 1) else 1 | |
223 | d = self.databyte >> 1 | |
224 | elif self.state == FIND_DATA: | |
225 | d = self.databyte | |
226 | else: | |
227 | # TODO: Error? | |
228 | pass | |
229 | ||
230 | # Last bit that came in was the ACK/NACK bit (1 = NACK). | |
231 | ack_bit = 'NACK' if (sda == 1) else 'ACK' | |
232 | ||
233 | if self.state == FIND_ADDRESS and self.wr == 1: | |
234 | cmd = 'ADDRESS_WRITE' | |
235 | elif self.state == FIND_ADDRESS and self.wr == 0: | |
236 | cmd = 'ADDRESS_READ' | |
237 | elif self.state == FIND_DATA and self.wr == 1: | |
238 | cmd = 'DATA_WRITE' | |
239 | elif self.state == FIND_DATA and self.wr == 0: | |
240 | cmd = 'DATA_READ' | |
241 | ||
242 | self.put(self.out_proto, [cmd, d, ack_bit]) | |
243 | self.put(self.out_ann, [ANN_SHIFTED, | |
244 | [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]]) | |
245 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, | |
246 | [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]]) | |
247 | ||
248 | self.bitcount = self.databyte = 0 | |
249 | self.startsample = -1 | |
250 | ||
251 | if self.state == FIND_ADDRESS: | |
252 | self.state = FIND_DATA | |
253 | elif self.state == FIND_DATA: | |
254 | # There could be multiple data bytes in a row. | |
255 | # So, either find a STOP condition or another data byte next. | |
256 | pass | |
257 | ||
258 | def found_stop(self, scl, sda): | |
259 | self.put(self.out_proto, ['STOP', None, None]) | |
260 | self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]]) | |
261 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]]) | |
262 | ||
263 | self.state = FIND_START | |
264 | self.is_repeat_start = 0 | |
265 | self.wr = -1 | |
266 | ||
267 | def put(self, output_id, data): | |
268 | # Inject sample range into the call up to sigrok. | |
269 | # TODO: 0-0 sample range for now. | |
270 | super(Decoder, self).put(0, 0, output_id, data) | |
271 | ||
272 | def decode(self, timeoffset, duration, data): | |
273 | for samplenum, (scl, sda) in data: | |
274 | self.samplecnt += 1 | |
275 | ||
276 | # First sample: Save SCL/SDA value. | |
277 | if self.oldscl == None: | |
278 | self.oldscl = scl | |
279 | self.oldsda = sda | |
280 | continue | |
281 | ||
282 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? | |
283 | ||
284 | # State machine. | |
285 | if self.state == FIND_START: | |
286 | if self.is_start_condition(scl, sda): | |
287 | self.found_start(scl, sda) | |
288 | elif self.state == FIND_ADDRESS: | |
289 | if self.is_data_bit(scl, sda): | |
290 | self.found_address_or_data(scl, sda) | |
291 | elif self.state == FIND_DATA: | |
292 | if self.is_data_bit(scl, sda): | |
293 | self.found_address_or_data(scl, sda) | |
294 | elif self.is_start_condition(scl, sda): | |
295 | self.found_start(scl, sda) | |
296 | elif self.is_stop_condition(scl, sda): | |
297 | self.found_stop(scl, sda) | |
298 | else: | |
299 | # TODO: Error? | |
300 | pass | |
301 | ||
302 | # Save current SDA/SCL values for the next round. | |
303 | self.oldscl = scl | |
304 | self.oldsda = sda | |
305 |