[libsigrokdecode.git] / decoders / can / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 3
    id = 'can'
    name = 'CAN'
    longname = 'Controller Area Network'
    desc = 'Field bus protocol for distributed realtime control.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['can']
    channels = (
        {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
    )
    options = (
        {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000},
        {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
    )
    annotations = (
        ('data', 'CAN payload data'),
        ('sof', 'Start of frame'),
        ('eof', 'End of frame'),
        ('id', 'Identifier'),
        ('ext-id', 'Extended identifier'),
        ('full-id', 'Full identifier'),
        ('ide', 'Identifier extension bit'),
        ('reserved-bit', 'Reserved bit 0 and 1'),
        ('rtr', 'Remote transmission request'),
        ('srr', 'Substitute remote request'),
        ('dlc', 'Data length count'),
        ('crc-sequence', 'CRC sequence'),
        ('crc-delimiter', 'CRC delimiter'),
        ('ack-slot', 'ACK slot'),
        ('ack-delimiter', 'ACK delimiter'),
        ('stuff-bit', 'Stuff bit'),
        ('warnings', 'Human-readable warnings'),
        ('bit', 'Bit'),
    )
    annotation_rows = (
        ('bits', 'Bits', (15, 17)),
        ('fields', 'Fields', tuple(range(15))),
        ('warnings', 'Warnings', (16,)),
    )

    def __init__(self):
        self.samplerate = None
        self.reset_variables()

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value
            self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
            self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']

    # Generic helper for CAN bit annotations.
    def putg(self, ss, es, data):
        left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
        self.put(ss - left, es + right, self.out_ann, data)

    # Single-CAN-bit annotation using the current samplenum.
    def putx(self, data):
        self.putg(self.samplenum, self.samplenum, data)

    # Single-CAN-bit annotation using the samplenum of CAN bit 12.
    def put12(self, data):
        self.putg(self.ss_bit12, self.ss_bit12, data)

    # Multi-CAN-bit annotation from self.ss_block to current samplenum.
    def putb(self, data):
        self.putg(self.ss_block, self.samplenum, data)

    def reset_variables(self):
        self.state = 'IDLE'
        self.sof = self.frame_type = self.dlc = None
        self.rawbits = [] # All bits, including stuff bits
        self.bits = [] # Only actual CAN frame bits (no stuff bits)
        self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF)
        self.last_databit = 999 # Positive value that bitnum+x will never match
        self.ss_block = None
        self.ss_bit12 = None
        self.ss_databytebits = []

    # Determine the position of the next desired bit's sample point.
    def get_sample_point(self, bitnum):
        samplenum = int(self.sof + (self.bit_width * bitnum) + self.sample_point)
        return samplenum

    def is_stuff_bit(self):
        # CAN uses NRZ encoding and bit stuffing.
        # After 5 identical bits, a stuff bit of opposite value is added.
        # But not in the CRC delimiter, ACK, and end of frame fields.
        if len(self.bits) > self.last_databit + 16:
            return False
        last_6_bits = self.rawbits[-6:]
        if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
            return False

        # Stuff bit. Keep it in self.rawbits, but drop it from self.bits.
        self.bits.pop() # Drop last bit.
        return True

    def is_valid_crc(self, crc_bits):
        return True # TODO

    def decode_error_frame(self, bits):
        pass # TODO

    def decode_overload_frame(self, bits):
        pass # TODO

    # Both standard and extended frames end with CRC, CRC delimiter, ACK,
    # ACK delimiter, and EOF fields. Handle them in a common function.
    # Returns True if the frame ended (EOF), False otherwise.
    def decode_frame_end(self, can_rx, bitnum):

        # Remember start of CRC sequence (see below).
        if bitnum == (self.last_databit + 1):
            self.ss_block = self.samplenum

        # CRC sequence (15 bits)
        elif bitnum == (self.last_databit + 15):
            x = self.last_databit + 1
            crc_bits = self.bits[x:x + 15 + 1]
            self.crc = int(''.join(str(d) for d in crc_bits), 2)
            self.putb([11, ['CRC sequence: 0x%04x' % self.crc,
                            'CRC: 0x%04x' % self.crc, 'CRC']])
            if not self.is_valid_crc(crc_bits):
                self.putb([16, ['CRC is invalid']])

        # CRC delimiter bit (recessive)
        elif bitnum == (self.last_databit + 16):
            self.putx([12, ['CRC delimiter: %d' % can_rx,
                            'CRC d: %d' % can_rx, 'CRC d']])
            if can_rx != 1:
                self.putx([16, ['CRC delimiter must be a recessive bit']])

        # ACK slot bit (dominant: ACK, recessive: NACK)
        elif bitnum == (self.last_databit + 17):
            ack = 'ACK' if can_rx == 0 else 'NACK'
            self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])

        # ACK delimiter bit (recessive)
        elif bitnum == (self.last_databit + 18):
            self.putx([14, ['ACK delimiter: %d' % can_rx,
                            'ACK d: %d' % can_rx, 'ACK d']])
            if can_rx != 1:
                self.putx([16, ['ACK delimiter must be a recessive bit']])

        # Remember start of EOF (see below).
        elif bitnum == (self.last_databit + 19):
            self.ss_block = self.samplenum

        # End of frame (EOF), 7 recessive bits
        elif bitnum == (self.last_databit + 25):
            self.putb([2, ['End of frame', 'EOF', 'E']])
            if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
                self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
            self.reset_variables()
            return True

        return False

    # Returns True if the frame ended (EOF), False otherwise.
    def decode_standard_frame(self, can_rx, bitnum):

        # Bit 14: RB0 (reserved bit)
        # Has to be sent dominant, but receivers should accept recessive too.
        if bitnum == 14:
            self.putx([7, ['Reserved bit 0: %d' % can_rx,
                           'RB0: %d' % can_rx, 'RB0']])

            # Bit 12: Remote transmission request (RTR) bit
            # Data frame: dominant, remote frame: recessive
            # Remote frames do not contain a data field.
            rtr = 'remote' if self.bits[12] == 1 else 'data'
            self.put12([8, ['Remote transmission request: %s frame' % rtr,
                            'RTR: %s frame' % rtr, 'RTR']])

        # Remember start of DLC (see below).
        elif bitnum == 15:
            self.ss_block = self.samplenum

        # Bits 15-18: Data length code (DLC), in number of bytes (0-8).
        elif bitnum == 18:
            self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2)
            self.putb([10, ['Data length code: %d' % self.dlc,
                            'DLC: %d' % self.dlc, 'DLC']])
            self.last_databit = 18 + (self.dlc * 8)
            if self.dlc > 8:
                self.putb([16, ['Data length code (DLC) > 8 is not allowed']])

        # Remember all databyte bits, except the very last one.
        elif bitnum in range(19, self.last_databit):
            self.ss_databytebits.append(self.samplenum)

        # Bits 19-X: Data field (0-8 bytes, depending on DLC)
        # The bits within a data byte are transferred MSB-first.
        elif bitnum == self.last_databit:
            self.ss_databytebits.append(self.samplenum) # Last databyte bit.
            for i in range(self.dlc):
                x = 18 + (8 * i) + 1
                b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
                ss = self.ss_databytebits[i * 8]
                es = self.ss_databytebits[((i + 1) * 8) - 1]
                self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
                                       'DB %d: 0x%02x' % (i, b), 'DB']])
            self.ss_databytebits = []

        elif bitnum > self.last_databit:
            return self.decode_frame_end(can_rx, bitnum)

        return False

    # Returns True if the frame ended (EOF), False otherwise.
    def decode_extended_frame(self, can_rx, bitnum):

        # Remember start of EID (see below).
        if bitnum == 14:
            self.ss_block = self.samplenum

        # Bits 14-31: Extended identifier (EID[17..0])
        elif bitnum == 31:
            self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
            s = '%d (0x%x)' % (self.eid, self.eid)
            self.putb([4, ['Extended Identifier: %s' % s,
                           'Extended ID: %s' % s, 'Extended ID', 'EID']])

            self.fullid = self.id << 18 | self.eid
            s = '%d (0x%x)' % (self.fullid, self.fullid)
            self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
                           'Full ID', 'FID']])

            # Bit 12: Substitute remote request (SRR) bit
            self.put12([9, ['Substitute remote request: %d' % self.bits[12],
                            'SRR: %d' % self.bits[12], 'SRR']])

        # Bit 32: Remote transmission request (RTR) bit
        # Data frame: dominant, remote frame: recessive
        # Remote frames do not contain a data field.
        if bitnum == 32:
            rtr = 'remote' if can_rx == 1 else 'data'
            self.putx([8, ['Remote transmission request: %s frame' % rtr,
                           'RTR: %s frame' % rtr, 'RTR']])

        # Bit 33: RB1 (reserved bit)
        elif bitnum == 33:
            self.putx([7, ['Reserved bit 1: %d' % can_rx,
                           'RB1: %d' % can_rx, 'RB1']])

        # Bit 34: RB0 (reserved bit)
        elif bitnum == 34:
            self.putx([7, ['Reserved bit 0: %d' % can_rx,
                           'RB0: %d' % can_rx, 'RB0']])

        # Remember start of DLC (see below).
        elif bitnum == 35:
            self.ss_block = self.samplenum

        # Bits 35-38: Data length code (DLC), in number of bytes (0-8).
        elif bitnum == 38:
            self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2)
            self.putb([10, ['Data length code: %d' % self.dlc,
                            'DLC: %d' % self.dlc, 'DLC']])
            self.last_databit = 38 + (self.dlc * 8)

        # Remember all databyte bits, except the very last one.
        elif bitnum in range(39, self.last_databit):
            self.ss_databytebits.append(self.samplenum)

        # Bits 39-X: Data field (0-8 bytes, depending on DLC)
        # The bits within a data byte are transferred MSB-first.
        elif bitnum == self.last_databit:
            self.ss_databytebits.append(self.samplenum) # Last databyte bit.
            for i in range(self.dlc):
                x = 38 + (8 * i) + 1
                b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
                ss = self.ss_databytebits[i * 8]
                es = self.ss_databytebits[((i + 1) * 8) - 1]
                self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
                                       'DB %d: 0x%02x' % (i, b), 'DB']])
            self.ss_databytebits = []

        elif bitnum > self.last_databit:
            return self.decode_frame_end(can_rx, bitnum)

        return False

    def handle_bit(self, can_rx):
        self.rawbits.append(can_rx)
        self.bits.append(can_rx)

        # Get the index of the current CAN frame bit (without stuff bits).
        bitnum = len(self.bits) - 1

        # If this is a stuff bit, remove it from self.bits and ignore it.
        if self.is_stuff_bit():
            self.putx([15, [str(can_rx)]])
            self.curbit += 1 # Increase self.curbit (bitnum is not affected).
            return
        else:
            self.putx([17, [str(can_rx)]])

        # Bit 0: Start of frame (SOF) bit
        if bitnum == 0:
            self.putx([1, ['Start of frame', 'SOF', 'S']])
            if can_rx != 0:
                self.putx([16, ['Start of frame (SOF) must be a dominant bit']])

        # Remember start of ID (see below).
        elif bitnum == 1:
            self.ss_block = self.samplenum

        # Bits 1-11: Identifier (ID[10..0])
        # The bits ID[10..4] must NOT be all recessive.
        elif bitnum == 11:
            self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
            s = '%d (0x%x)' % (self.id, self.id),
            self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
            if (self.id & 0x7f0) == 0x7f0:
                self.putb([16, ['Identifier bits 10..4 must not be all recessive']])

        # RTR or SRR bit, depending on frame type (gets handled later).
        elif bitnum == 12:
            # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only.
            self.ss_bit12 = self.samplenum

        # Bit 13: Identifier extension (IDE) bit
        # Standard frame: dominant, extended frame: recessive
        elif bitnum == 13:
            ide = self.frame_type = 'standard' if can_rx == 0 else 'extended'
            self.putx([6, ['Identifier extension bit: %s frame' % ide,
                           'IDE: %s frame' % ide, 'IDE']])

        # Bits 14-X: Frame-type dependent, passed to the resp. handlers.
        elif bitnum >= 14:
            if self.frame_type == 'standard':
                done = self.decode_standard_frame(can_rx, bitnum)
            else:
                done = self.decode_extended_frame(can_rx, bitnum)

            # The handlers return True if a frame ended (EOF).
            if done:
                return

        # After a frame there are 3 intermission bits (recessive).
        # After these bits, the bus is considered free.

        self.curbit += 1

    def decode(self):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')

        while True:
            # State machine.
            if self.state == 'IDLE':
                # Wait for a dominant state (logic 0) on the bus.
                (can_rx,) = self.wait({0: 'l'})
                self.sof = self.samplenum
                self.state = 'GET BITS'
            elif self.state == 'GET BITS':
                # Wait until we're in the correct bit/sampling position.
                pos = self.get_sample_point(self.curbit)
                (can_rx,) = self.wait({'skip': pos - self.samplenum})
                self.handle_bit(can_rx)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
	21
	22	class SamplerateError(Exception):
	23	pass
	24
	25	class Decoder(srd.Decoder):
	26	api_version = 3
	27	id = 'can'
	28	name = 'CAN'
	29	longname = 'Controller Area Network'
	30	desc = 'Field bus protocol for distributed realtime control.'
	31	license = 'gplv2+'
	32	inputs = ['logic']
	33	outputs = ['can']
	34	channels = (
	35	{'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
	36	)
	37	options = (
	38	{'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000},
	39	{'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
	40	)
	41	annotations = (
	42	('data', 'CAN payload data'),
	43	('sof', 'Start of frame'),
	44	('eof', 'End of frame'),
	45	('id', 'Identifier'),
	46	('ext-id', 'Extended identifier'),
	47	('full-id', 'Full identifier'),
	48	('ide', 'Identifier extension bit'),
	49	('reserved-bit', 'Reserved bit 0 and 1'),
	50	('rtr', 'Remote transmission request'),
	51	('srr', 'Substitute remote request'),
	52	('dlc', 'Data length count'),
	53	('crc-sequence', 'CRC sequence'),
	54	('crc-delimiter', 'CRC delimiter'),
	55	('ack-slot', 'ACK slot'),
	56	('ack-delimiter', 'ACK delimiter'),
	57	('stuff-bit', 'Stuff bit'),
	58	('warnings', 'Human-readable warnings'),
	59	('bit', 'Bit'),
	60	)
	61	annotation_rows = (
	62	('bits', 'Bits', (15, 17)),
	63	('fields', 'Fields', tuple(range(15))),
	64	('warnings', 'Warnings', (16,)),
	65	)
	66
	67	def __init__(self):
	68	self.samplerate = None
	69	self.reset_variables()
	70
	71	def start(self):
	72	self.out_ann = self.register(srd.OUTPUT_ANN)
	73
	74	def metadata(self, key, value):
	75	if key == srd.SRD_CONF_SAMPLERATE:
	76	self.samplerate = value
	77	self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
	78	self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
	79
	80	# Generic helper for CAN bit annotations.
	81	def putg(self, ss, es, data):
	82	left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
	83	self.put(ss - left, es + right, self.out_ann, data)
	84
	85	# Single-CAN-bit annotation using the current samplenum.
	86	def putx(self, data):
	87	self.putg(self.samplenum, self.samplenum, data)
	88
	89	# Single-CAN-bit annotation using the samplenum of CAN bit 12.
	90	def put12(self, data):
	91	self.putg(self.ss_bit12, self.ss_bit12, data)
	92
	93	# Multi-CAN-bit annotation from self.ss_block to current samplenum.
	94	def putb(self, data):
	95	self.putg(self.ss_block, self.samplenum, data)
	96
	97	def reset_variables(self):
	98	self.state = 'IDLE'
	99	self.sof = self.frame_type = self.dlc = None
	100	self.rawbits = [] # All bits, including stuff bits
	101	self.bits = [] # Only actual CAN frame bits (no stuff bits)
	102	self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF)
	103	self.last_databit = 999 # Positive value that bitnum+x will never match
	104	self.ss_block = None
	105	self.ss_bit12 = None
	106	self.ss_databytebits = []
	107
	108	# Determine the position of the next desired bit's sample point.
	109	def get_sample_point(self, bitnum):
	110	samplenum = int(self.sof + (self.bit_width * bitnum) + self.sample_point)
	111	return samplenum
	112
	113	def is_stuff_bit(self):
	114	# CAN uses NRZ encoding and bit stuffing.
	115	# After 5 identical bits, a stuff bit of opposite value is added.
	116	# But not in the CRC delimiter, ACK, and end of frame fields.
	117	if len(self.bits) > self.last_databit + 16:
	118	return False
	119	last_6_bits = self.rawbits[-6:]
	120	if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
	121	return False
	122
	123	# Stuff bit. Keep it in self.rawbits, but drop it from self.bits.
	124	self.bits.pop() # Drop last bit.
	125	return True
	126
	127	def is_valid_crc(self, crc_bits):
	128	return True # TODO
	129
	130	def decode_error_frame(self, bits):
	131	pass # TODO
	132
	133	def decode_overload_frame(self, bits):
	134	pass # TODO
	135
	136	# Both standard and extended frames end with CRC, CRC delimiter, ACK,
	137	# ACK delimiter, and EOF fields. Handle them in a common function.
	138	# Returns True if the frame ended (EOF), False otherwise.
	139	def decode_frame_end(self, can_rx, bitnum):
	140
	141	# Remember start of CRC sequence (see below).
	142	if bitnum == (self.last_databit + 1):
	143	self.ss_block = self.samplenum
	144
	145	# CRC sequence (15 bits)
	146	elif bitnum == (self.last_databit + 15):
	147	x = self.last_databit + 1
	148	crc_bits = self.bits[x:x + 15 + 1]
	149	self.crc = int(''.join(str(d) for d in crc_bits), 2)
	150	self.putb([11, ['CRC sequence: 0x%04x' % self.crc,
	151	'CRC: 0x%04x' % self.crc, 'CRC']])
	152	if not self.is_valid_crc(crc_bits):
	153	self.putb([16, ['CRC is invalid']])
	154
	155	# CRC delimiter bit (recessive)
	156	elif bitnum == (self.last_databit + 16):
	157	self.putx([12, ['CRC delimiter: %d' % can_rx,
	158	'CRC d: %d' % can_rx, 'CRC d']])
	159	if can_rx != 1:
	160	self.putx([16, ['CRC delimiter must be a recessive bit']])
	161
	162	# ACK slot bit (dominant: ACK, recessive: NACK)
	163	elif bitnum == (self.last_databit + 17):
	164	ack = 'ACK' if can_rx == 0 else 'NACK'
	165	self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])
	166
	167	# ACK delimiter bit (recessive)
	168	elif bitnum == (self.last_databit + 18):
	169	self.putx([14, ['ACK delimiter: %d' % can_rx,
	170	'ACK d: %d' % can_rx, 'ACK d']])
	171	if can_rx != 1:
	172	self.putx([16, ['ACK delimiter must be a recessive bit']])
	173
	174	# Remember start of EOF (see below).
	175	elif bitnum == (self.last_databit + 19):
	176	self.ss_block = self.samplenum
	177
	178	# End of frame (EOF), 7 recessive bits
	179	elif bitnum == (self.last_databit + 25):
	180	self.putb([2, ['End of frame', 'EOF', 'E']])
	181	if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
	182	self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
	183	self.reset_variables()
	184	return True
	185
	186	return False
	187
	188	# Returns True if the frame ended (EOF), False otherwise.
	189	def decode_standard_frame(self, can_rx, bitnum):
	190
	191	# Bit 14: RB0 (reserved bit)
	192	# Has to be sent dominant, but receivers should accept recessive too.
	193	if bitnum == 14:
	194	self.putx([7, ['Reserved bit 0: %d' % can_rx,
	195	'RB0: %d' % can_rx, 'RB0']])
	196
	197	# Bit 12: Remote transmission request (RTR) bit
	198	# Data frame: dominant, remote frame: recessive
	199	# Remote frames do not contain a data field.
	200	rtr = 'remote' if self.bits[12] == 1 else 'data'
	201	self.put12([8, ['Remote transmission request: %s frame' % rtr,
	202	'RTR: %s frame' % rtr, 'RTR']])
	203
	204	# Remember start of DLC (see below).
	205	elif bitnum == 15:
	206	self.ss_block = self.samplenum
	207
	208	# Bits 15-18: Data length code (DLC), in number of bytes (0-8).
	209	elif bitnum == 18:
	210	self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2)
	211	self.putb([10, ['Data length code: %d' % self.dlc,
	212	'DLC: %d' % self.dlc, 'DLC']])
	213	self.last_databit = 18 + (self.dlc * 8)
	214	if self.dlc > 8:
	215	self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
	216
	217	# Remember all databyte bits, except the very last one.
	218	elif bitnum in range(19, self.last_databit):
	219	self.ss_databytebits.append(self.samplenum)
	220
	221	# Bits 19-X: Data field (0-8 bytes, depending on DLC)
	222	# The bits within a data byte are transferred MSB-first.
	223	elif bitnum == self.last_databit:
	224	self.ss_databytebits.append(self.samplenum) # Last databyte bit.
	225	for i in range(self.dlc):
	226	x = 18 + (8 * i) + 1
	227	b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
	228	ss = self.ss_databytebits[i * 8]
	229	es = self.ss_databytebits[((i + 1) * 8) - 1]
	230	self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
	231	'DB %d: 0x%02x' % (i, b), 'DB']])
	232	self.ss_databytebits = []
	233
	234	elif bitnum > self.last_databit:
	235	return self.decode_frame_end(can_rx, bitnum)
	236
	237	return False
	238
	239	# Returns True if the frame ended (EOF), False otherwise.
	240	def decode_extended_frame(self, can_rx, bitnum):
	241
	242	# Remember start of EID (see below).
	243	if bitnum == 14:
	244	self.ss_block = self.samplenum
	245
	246	# Bits 14-31: Extended identifier (EID[17..0])
	247	elif bitnum == 31:
	248	self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
	249	s = '%d (0x%x)' % (self.eid, self.eid)
	250	self.putb([4, ['Extended Identifier: %s' % s,
	251	'Extended ID: %s' % s, 'Extended ID', 'EID']])
	252
	253	self.fullid = self.id << 18 \| self.eid
	254	s = '%d (0x%x)' % (self.fullid, self.fullid)
	255	self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
	256	'Full ID', 'FID']])
	257
	258	# Bit 12: Substitute remote request (SRR) bit
	259	self.put12([9, ['Substitute remote request: %d' % self.bits[12],
	260	'SRR: %d' % self.bits[12], 'SRR']])
	261
	262	# Bit 32: Remote transmission request (RTR) bit
	263	# Data frame: dominant, remote frame: recessive
	264	# Remote frames do not contain a data field.
	265	if bitnum == 32:
	266	rtr = 'remote' if can_rx == 1 else 'data'
	267	self.putx([8, ['Remote transmission request: %s frame' % rtr,
	268	'RTR: %s frame' % rtr, 'RTR']])
	269
	270	# Bit 33: RB1 (reserved bit)
	271	elif bitnum == 33:
	272	self.putx([7, ['Reserved bit 1: %d' % can_rx,
	273	'RB1: %d' % can_rx, 'RB1']])
	274
	275	# Bit 34: RB0 (reserved bit)
	276	elif bitnum == 34:
	277	self.putx([7, ['Reserved bit 0: %d' % can_rx,
	278	'RB0: %d' % can_rx, 'RB0']])
	279
	280	# Remember start of DLC (see below).
	281	elif bitnum == 35:
	282	self.ss_block = self.samplenum
	283
	284	# Bits 35-38: Data length code (DLC), in number of bytes (0-8).
	285	elif bitnum == 38:
	286	self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2)
	287	self.putb([10, ['Data length code: %d' % self.dlc,
	288	'DLC: %d' % self.dlc, 'DLC']])
	289	self.last_databit = 38 + (self.dlc * 8)
	290
	291	# Remember all databyte bits, except the very last one.
	292	elif bitnum in range(39, self.last_databit):
	293	self.ss_databytebits.append(self.samplenum)
	294
	295	# Bits 39-X: Data field (0-8 bytes, depending on DLC)
	296	# The bits within a data byte are transferred MSB-first.
	297	elif bitnum == self.last_databit:
	298	self.ss_databytebits.append(self.samplenum) # Last databyte bit.
	299	for i in range(self.dlc):
	300	x = 38 + (8 * i) + 1
	301	b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
	302	ss = self.ss_databytebits[i * 8]
	303	es = self.ss_databytebits[((i + 1) * 8) - 1]
	304	self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
	305	'DB %d: 0x%02x' % (i, b), 'DB']])
	306	self.ss_databytebits = []
	307
	308	elif bitnum > self.last_databit:
	309	return self.decode_frame_end(can_rx, bitnum)
	310
	311	return False
	312
	313	def handle_bit(self, can_rx):
	314	self.rawbits.append(can_rx)
	315	self.bits.append(can_rx)
	316
	317	# Get the index of the current CAN frame bit (without stuff bits).
	318	bitnum = len(self.bits) - 1
	319
	320	# If this is a stuff bit, remove it from self.bits and ignore it.
	321	if self.is_stuff_bit():
	322	self.putx([15, [str(can_rx)]])
	323	self.curbit += 1 # Increase self.curbit (bitnum is not affected).
	324	return
	325	else:
	326	self.putx([17, [str(can_rx)]])
	327
	328	# Bit 0: Start of frame (SOF) bit
	329	if bitnum == 0:
	330	self.putx([1, ['Start of frame', 'SOF', 'S']])
	331	if can_rx != 0:
	332	self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
	333
	334	# Remember start of ID (see below).
	335	elif bitnum == 1:
	336	self.ss_block = self.samplenum
	337
	338	# Bits 1-11: Identifier (ID[10..0])
	339	# The bits ID[10..4] must NOT be all recessive.
	340	elif bitnum == 11:
	341	self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
	342	s = '%d (0x%x)' % (self.id, self.id),
	343	self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
	344	if (self.id & 0x7f0) == 0x7f0:
	345	self.putb([16, ['Identifier bits 10..4 must not be all recessive']])
	346
	347	# RTR or SRR bit, depending on frame type (gets handled later).
	348	elif bitnum == 12:
	349	# self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only.
	350	self.ss_bit12 = self.samplenum
	351
	352	# Bit 13: Identifier extension (IDE) bit
	353	# Standard frame: dominant, extended frame: recessive
	354	elif bitnum == 13:
	355	ide = self.frame_type = 'standard' if can_rx == 0 else 'extended'
	356	self.putx([6, ['Identifier extension bit: %s frame' % ide,
	357	'IDE: %s frame' % ide, 'IDE']])
	358
	359	# Bits 14-X: Frame-type dependent, passed to the resp. handlers.
	360	elif bitnum >= 14:
	361	if self.frame_type == 'standard':
	362	done = self.decode_standard_frame(can_rx, bitnum)
	363	else:
	364	done = self.decode_extended_frame(can_rx, bitnum)
	365
	366	# The handlers return True if a frame ended (EOF).
	367	if done:
	368	return
	369
	370	# After a frame there are 3 intermission bits (recessive).
	371	# After these bits, the bus is considered free.
	372
	373	self.curbit += 1
	374
	375	def decode(self):
	376	if not self.samplerate:
	377	raise SamplerateError('Cannot decode without samplerate.')
	378
	379	while True:
	380	# State machine.
	381	if self.state == 'IDLE':
	382	# Wait for a dominant state (logic 0) on the bus.
	383	(can_rx,) = self.wait({0: 'l'})
	384	self.sof = self.samplenum
	385	self.state = 'GET BITS'
	386	elif self.state == 'GET BITS':
	387	# Wait until we're in the correct bit/sampling position.
	388	pos = self.get_sample_point(self.curbit)
	389	(can_rx,) = self.wait({'skip': pos - self.samplenum})
	390	self.handle_bit(can_rx)