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I2C decoder format draft (unfinished).
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1##
2## This file is part of the sigrok project.
3##
4## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
21#
22# I2C protocol decoder
23#
24
25#
26# The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
27# bus using two signals (SCL = serial clock line, SDA = serial data line).
28#
29# There can be many devices on the same bus. Each device can potentially be
30# master or slave (and that can change during runtime). Both slave and master
31# can potentially play the transmitter or receiver role (this can also
32# change at runtime).
33#
34# Possible maximum data rates:
35# - Standard mode: 100 kbit/s
36# - Fast mode: 400 kbit/s
37# - Fast-mode Plus: 1 Mbit/s
38# - High-speed mode: 3.4 Mbit/s
39#
40# START condition (S): SDA = falling, SCL = high
41# Repeated START condition (Sr): same as S
42# STOP condition (P): SDA = rising, SCL = high
43#
33e72c54 44# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
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45# Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
46# that indicates an ACK, if it's high that indicates a NACK.
47#
48# After the first START condition, a master sends the device address of the
49# slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
33e72c54 50# After those 7 bits, a data direction bit is sent. If the bit is low that
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51# indicates a WRITE operation, if it's high that indicates a READ operation.
52#
53# Later an optional 10bit slave addressing scheme was added.
54#
55# Documentation:
56# http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
57# http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
58# http://en.wikipedia.org/wiki/I2C
59#
60
61# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
62# TODO: Handle clock stretching.
63# TODO: Handle combined messages / repeated START.
64# TODO: Implement support for 7bit and 10bit slave addresses.
65# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
66# TODO: Implement support for detecting various bus errors.
67
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68#
69# I2C output format:
70#
71# The output consists of a (Python) list of I2C "packets", each of which
72# has an (implicit) index number (its index in the list).
73# Each packet consists of a Python dict with certain key/value pairs.
74#
75# TODO: Make this a list later instead of a dict?
76#
77# 'type': (string)
78# - 'S' (START condition)
79# - 'Sr' (Repeated START)
80# - 'AR' (Address, read)
81# - 'AW' (Address, write)
82# - 'DR' (Data, read)
83# - 'DW' (Data, write)
84# - 'P' (STOP condition)
85# 'range': (tuple of 2 integers, the min/max samplenumber of this range)
86# - (min, max)
87# - min/max can also be identical.
88# 'data': (actual data as integer ???) TODO: This can be very variable...
89# 'ann': (string; additional annotations / comments)
90#
91# Example output:
92# [{'type': 'S', 'range': (150, 160), 'data': None, 'ann': 'Foobar'},
93# {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'},
94# {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'},
95# {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'},
96# {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'},
97# {'type': 'P', 'range': (650, 660), 'data': None, 'ann': None}]
98#
99# Possible other events:
100# - Error event in case protocol looks broken:
101# [{'type': 'ERROR', 'range': (min, max),
102# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
103# [{'type': 'ERROR', 'range': (min, max),
104# 'data': TODO, 'ann': 'TODO'},
105# - TODO: Make list of possible errors accessible as metadata?
106#
107# TODO: I2C address of slaves.
108# TODO: Handle multiple different I2C devices on same bus
109# -> we need to decode multiple protocols at the same time.
110# TODO: range: Always contiguous? Splitted ranges? Multiple per event?
111#
112
113#
114# I2C input format:
115#
116# signals:
117# [[id, channel, description], ...] # TODO
118#
119# Example:
120# {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'}
121# {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'}
122# ...
123#
124# {'inbuf': [...],
125# 'signals': [{'SCL': }]}
126#
127
5c55017c 128def decode(inbuf):
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129 """I2C protocol decoder"""
130
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131 # FIXME: Get the data in the correct format in the first place.
132 inbuf = [ord(x) for x in inbuf]
133
0588ed70 134 # FIXME: This should be passed in as metadata, not hardcoded here.
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135 metadata = {
136 'numchannels': 8,
137 'signals': {
138 'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'},
139 'sda': {'ch': 7, 'name': 'SDA' 'desc': 'Serial data line'},
140 },
141 }
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142
143 o = wr = ack = d = ''
144 bitcount = data = 0
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145 IDLE, START, ADDRESS, DATA = range(4)
146 state = IDLE
0588ed70 147
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148 # Get the channel/probe number of the SCL/SDA signals.
149 scl_bit = metadata['signals']['scl']['ch']
150 sda_bit = metadata['signals']['sda']['ch']
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151
152 # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
a156f09e 153 s = inbuf[0]
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154 oldscl = (s & (1 << scl_bit)) >> scl_bit
155 oldsda = (s & (1 << sda_bit)) >> sda_bit
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156
157 # Loop over all samples.
158 # TODO: Handle LAs with more/less than 8 channels.
159 for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
0588ed70 160 # Get SCL/SDA bit values (0/1 for low/high).
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161 scl = (s & (1 << scl_bit)) >> scl_bit
162 sda = (s & (1 << sda_bit)) >> sda_bit
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163
164 # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
165
166 # START condition (S): SDA = falling, SCL = high
167 if (oldsda == 1 and sda == 0) and scl == 1:
168 o += "%d\t\tSTART\n" % samplenum
33e72c54 169 state = ADDRESS
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170 bitcount = data = 0
171
172 # Data latching by transmitter: SCL = low
173 elif (scl == 0):
174 pass # TODO
175
176 # Data sampling of receiver: SCL = rising
177 elif (oldscl == 0 and scl == 1):
178 bitcount += 1
179
180 # o += "%d\t\tRECEIVED BIT %d: %d\n" % \
181 # (samplenum, 8 - bitcount, sda)
182
183 # Address and data are transmitted MSB-first.
184 data <<= 1
185 data |= sda
186
187 if bitcount != 9:
188 continue
189
190 # We received 8 address/data bits and the ACK/NACK bit.
191 data >>= 1 # Shift out unwanted ACK/NACK bit here.
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192 # o += "%d\t\t%s: " % (samplenum, state)
193 o += "%d\t\tTODO:STATE: " % samplenum
0588ed70 194 ack = (sda == 1) and 'NACK' or 'ACK'
33e72c54 195 d = (state == ADDRESS) and (data & 0xfe) or data
0588ed70 196 wr = ''
33e72c54 197 if state == ADDRESS:
0588ed70 198 wr = (data & 1) and ' (W)' or ' (R)'
33e72c54 199 state = DATA
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200 o += "0x%02x%s (%s)\n" % (d, wr, ack)
201 bitcount = data = 0
202
203 # STOP condition (P): SDA = rising, SCL = high
204 elif (oldsda == 0 and sda == 1) and scl == 1:
205 o += "%d\t\tSTOP\n" % samplenum
33e72c54 206 state = IDLE
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207
208 # Save current SDA/SCL values for the next round.
209 oldscl = scl
210 oldsda = sda
211
212 return o
213
23a13b21 214def register():
215 return {
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216 'id': 'i2c',
217 'name': 'I2C',
5c55017c 218 'desc': 'Inter-Integrated Circuit (I2C) bus',
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219 'inputformats': ['raw'],
220 'signalnames': {
221 'SCL': 'Serial clock line',
222 'SDA': 'Serial data line',
223 },
a156f09e 224 'outputformats': ['i2c'],
0588ed70 225 }
0588ed70 226
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227# Use psyco (if available) as it results in huge performance improvements.
228try:
229 import psyco
5c55017c 230 psyco.bind(decode)
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231except ImportError:
232 pass
233