]> sigrok.org Git - libsigrokdecode.git/blame - decoders/spiflash/lists.py
dmx512: remove previous implementation before replacing it
[libsigrokdecode.git] / decoders / spiflash / lists.py
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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2015 Uwe Hermann <uwe@hermann-uwe.de>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
4539e9ca 17## along with this program; if not, see <http://www.gnu.org/licenses/>.
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18##
19
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20from collections import OrderedDict
21
22# OrderedDict which maps command IDs to their names and descriptions.
23# Please keep this sorted by command ID.
24# Don't forget to update 'Ann' in pd.py if you add/remove items here.
25cmds = OrderedDict([
26 (0x01, ('WRSR', 'Write status register')),
27 (0x02, ('PP', 'Page program')),
28 (0x03, ('READ', 'Read data')),
29 (0x04, ('WRDI', 'Write disable')),
30 (0x05, ('RDSR', 'Read status register')),
31 (0x06, ('WREN', 'Write enable')),
32 (0x0b, ('FAST/READ', 'Fast read data')),
33 (0x20, ('SE', 'Sector erase')),
34 (0x2b, ('RDSCUR', 'Read security register')),
35 (0x2f, ('WRSCUR', 'Write security register')),
36 (0x35, ('RDSR2', 'Read status register 2')),
37 (0x60, ('CE', 'Chip erase')),
38 (0x70, ('ESRY', 'Enable SO to output RY/BY#')),
39 (0x80, ('DSRY', 'Disable SO to output RY/BY#')),
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40 (0x82, ('WRITE1', 'Main memory page program through buffer 1 with built-in erase')),
41 (0x85, ('WRITE2', 'Main memory page program through buffer 2 with built-in erase')),
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42 (0x90, ('REMS', 'Read electronic manufacturer & device ID')),
43 (0x9f, ('RDID', 'Read identification')),
44 (0xab, ('RDP/RES', 'Release from deep powerdown / Read electronic ID')),
45 (0xad, ('CP', 'Continuously program mode')),
46 (0xb1, ('ENSO', 'Enter secured OTP')),
47 (0xb9, ('DP', 'Deep power down')),
de22de7f 48 (0xbb, ('2READ', '2x I/O read')), # a.k.a. "Fast read dual I/O".
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49 (0xc1, ('EXSO', 'Exit secured OTP')),
50 (0xc7, ('CE2', 'Chip erase')), # Alternative command ID
8a73c6c7 51 (0xd7, ('STATUS', 'Status register read')),
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52 (0xd8, ('BE', 'Block erase')),
53 (0xef, ('REMS2', 'Read ID for 2x I/O mode')),
54])
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55
56device_name = {
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57 'adesto': {
58 0x00: 'AT45Dxxx family, standard series',
59 },
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60 'fidelix': {
61 0x15: 'FM25Q32',
62 },
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63 'macronix': {
64 0x14: 'MX25L1605D',
65 0x15: 'MX25L3205D',
66 0x16: 'MX25L6405D',
67 },
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68 'winbond': {
69 0x13: 'W25Q80DV',
70 },
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71}
72
73chips = {
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74 # Adesto
75 'adesto_at45db161e': {
76 'vendor': 'Adesto',
77 'model': 'AT45DB161E',
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78 'res_id': None, # The chip doesn't emit an ID here.
79 'rems_id': None, # Not supported by the chip.
80 'rems2_id': None, # Not supported by the chip.
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81 'rdid_id': 0x1f26000100, # RDID and 2 extra "EDI" bytes.
82 'page_size': 528, # Configurable, could also be 512 bytes.
83 'sector_size': 128 * 1024,
84 'block_size': 4 * 1024,
85 },
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86 # Atmel
87 'atmel_at25128': {
88 'vendor': 'Atmel',
89 'model': 'AT25128',
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90 'res_id': None, # Not supported by the chip.
91 'rems_id': None, # Not supported by the chip.
92 'rems2_id': None, # Not supported by the chip.
93 'rdid_id': None, # Not supported by the chip.
35884460 94 'page_size': 64,
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95 'sector_size': None, # The chip doesn't have sectors.
96 'block_size': None, # The chip doesn't have blocks.
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97 },
98 'atmel_at25256': {
99 'vendor': 'Atmel',
100 'model': 'AT25256',
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101 'res_id': None, # Not supported by the chip.
102 'rems_id': None, # Not supported by the chip.
103 'rems2_id': None, # Not supported by the chip.
104 'rdid_id': None, # Not supported by the chip.
35884460 105 'page_size': 64,
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106 'sector_size': None, # The chip doesn't have sectors.
107 'block_size': None, # The chip doesn't have blocks.
35884460 108 },
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109 # FIDELIX
110 'fidelix_fm25q32': {
111 'vendor': 'FIDELIX',
112 'model': 'FM25Q32',
113 'res_id': 0x15,
114 'rems_id': 0xa115,
115 'rems2_id': 0xa115,
116 'rdid_id': 0xa14016,
117 'page_size': 256,
118 'sector_size': 4 * 1024,
119 'block_size': 64 * 1024,
120 },
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121 # Macronix
122 'macronix_mx25l1605d': {
123 'vendor': 'Macronix',
124 'model': 'MX25L1605D',
125 'res_id': 0x14,
126 'rems_id': 0xc214,
127 'rems2_id': 0xc214,
128 'rdid_id': 0xc22015,
129 'page_size': 256,
130 'sector_size': 4 * 1024,
131 'block_size': 64 * 1024,
132 },
133 'macronix_mx25l3205d': {
134 'vendor': 'Macronix',
135 'model': 'MX25L3205D',
136 'res_id': 0x15,
137 'rems_id': 0xc215,
138 'rems2_id': 0xc215,
139 'rdid_id': 0xc22016,
140 'page_size': 256,
141 'sector_size': 4 * 1024,
142 'block_size': 64 * 1024,
143 },
144 'macronix_mx25l6405d': {
145 'vendor': 'Macronix',
146 'model': 'MX25L6405D',
147 'res_id': 0x16,
148 'rems_id': 0xc216,
149 'rems2_id': 0xc216,
150 'rdid_id': 0xc22017,
151 'page_size': 256,
152 'sector_size': 4 * 1024,
153 'block_size': 64 * 1024,
154 },
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155 # Winbond
156 'winbond_w25q80dv': {
157 'vendor': 'Winbond',
158 'model': 'W25Q80DV',
159 'res_id': 0x13,
160 'rems_id': 0xef13,
b62ca656 161 'rems2_id': None, # Not supported by the chip.
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162 'rdid_id': 0xef4014,
163 'page_size': 256,
164 'sector_size': 4 * 1024,
165 'block_size': 64 * 1024, # Configurable, could also be 32 * 1024 bytes.
166 },
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