[libsigrokdecode.git] / decoders / rfm12 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2014 Sławek Piotrowski <sentinel@atteo.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd

class Decoder(srd.Decoder):
    api_version = 3
    id = 'rfm12'
    name = 'RFM12'
    longname = 'RFM12 control protocol'
    desc = 'HopeRF RFM12 wireless transceiver control protocol.'
    license = 'gplv2+'
    inputs = ['spi']
    outputs = ['rfm12']
    tags = ['Wireless/RF']
    annotations = (
        ('cmd', 'Command'),
        ('params', 'Command parameters'),
        ('disabled', 'Disabled bits'),
        ('return', 'Returned values'),
        ('disabled_return', 'Disabled returned values'),
        ('interpretation', 'Interpretation'),
    )
    annotation_rows = (
        ('commands', 'Commands', (0, 1, 2)),
        ('return', 'Return', (3, 4)),
        ('interpretation', 'Interpretation', (5,)),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.mosi_bytes, self.miso_bytes = [], []
        self.mosi_bits, self.miso_bits = [], []
        self.row_pos = [0, 0, 0]

        self.ann_to_row = [0, 0, 0, 1, 1, 2]

        # Initialize with Power-On-Reset values.
        self.last_status = [0x00, 0x00]
        self.last_config = 0x08
        self.last_power = 0x08
        self.last_freq = 0x680
        self.last_data_rate = 0x23
        self.last_fifo_and_reset = 0x80
        self.last_afc = 0xF7
        self.last_transceiver = 0x00
        self.last_pll = 0x77

    def advance_ann(self, ann, length):
        row = self.ann_to_row[ann]
        self.row_pos[row] += length

    def putx(self, ann, length, description):
        if not isinstance(description, list):
            description = [description]
        row = self.ann_to_row[ann]
        bit = self.row_pos[row]
        self.put(self.mosi_bits[bit][1], self.mosi_bits[bit + length - 1][2],
                 self.out_ann, [ann, description])
        bit += length
        self.row_pos[row] = bit

    def describe_bits(self, data, names):
        i = 0x01 << len(names) - 1
        bit = 0
        while i != 0:
            if names[bit] != '':
                self.putx(1 if (data & i) else 2, 1, names[bit])
            i >>= 1
            bit += 1

    def describe_return_bits(self, data, names):
        i = 0x01 << len(names) - 1
        bit = 0
        while i != 0:
            if names[bit] != '':
                self.putx(3 if (data & i) else 4, 1, names[bit])
            else:
                self.advance_ann(3, 1)
            i >>= 1
            bit += 1

    def describe_changed_bits(self, data, old_data, names):
        changes = data ^ old_data
        i = 0x01 << (len(names) - 1)
        bit = 0
        while i != 0:
            if names[bit] != '' and changes & i:
                s = ['+', 'Turning on'] if (data & i) else ['-', 'Turning off']
                self.putx(5, 1, s)
            else:
                self.advance_ann(5, 1)
            i >>= 1
            bit += 1

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def handle_configuration_cmd(self, cmd, ret):
        self.putx(0, 8, ['Configuration command', 'Configuration'])
        NAMES = [['Internal data register', 'el'], ['FIFO mode', 'ef']]

        bits = (cmd[1] & 0xC0) >> 6
        old_bits = (self.last_config & 0xC0) >> 6
        self.describe_bits(bits, NAMES)
        self.describe_changed_bits(bits, old_bits, NAMES)

        FREQUENCIES = ['315', '433', '868', '915']
        f = FREQUENCIES[(cmd[1] & 0x30) >> 4] + 'MHz'
        self.putx(1, 2, ['Frequency: ' + f, f])
        if cmd[1] & 0x30 != self.last_config & 0x30:
            self.putx(5, 2, ['Changed', '~'])

        c = '%.1fpF' % (8.5 + (cmd[1] & 0xF) * 0.5)
        self.putx(1, 4, ['Capacitance: ' + c, c])
        if cmd[1] & 0xF != self.last_config & 0xF:
            self.putx(5, 4, ['Changed', '~'])

        self.last_config = cmd[1]

    def handle_power_management_cmd(self, cmd, ret):
        self.putx(0, 8, ['Power management', 'Power'])
        NAMES = [['Receiver chain', 'er'], ['Baseband circuit', 'ebb'],
                 ['Transmission', 'et'], ['Synthesizer', 'es'],
                 ['Crystal oscillator', 'ex'], ['Low battery detector', 'eb'],
                 ['Wake-up timer', 'ew'], ['Clock output off switch', 'dc']]

        self.describe_bits(cmd[1], NAMES)

        power = cmd[1]

        # Some bits imply other, even if they are set to 0.
        if power & 0x80:
            power |= 0x58
        if power & 0x20:
            power |= 0x18
        self.describe_changed_bits(power, self.last_power, NAMES)

        self.last_power = power

    def handle_frequency_setting_cmd(self, cmd, ret):
        self.putx(0, 4, ['Frequency setting', 'Frequency'])
        f = ((cmd[1] & 0xF) << 8) + cmd[2]
        self.putx(0, 12, ['F = %3.4f' % f])
        self.row_pos[2] -= 4
        if self.last_freq != f:
            self.putx(5, 12, ['Changing', '~'])
        self.last_freq = f

    def handle_data_rate_cmd(self, cmd, ret):
        self.putx(0, 8, ['Data rate command', 'Data rate'])
        r = cmd[1] & 0x7F
        cs = (cmd[1] & 0x80) >> 7
        rate = 10000 / 29.0 / (r + 1) / (1 + 7 * cs)
        self.putx(0, 8, ['%3.1fkbps' % rate])
        if self.last_data_rate != cmd[1]:
            self.putx(5, 8, ['Changing', '~'])
        self.last_data_rate = cmd[1]

    def handle_receiver_control_cmd(self, cmd, ret):
        self.putx(0, 5, ['Receiver control command'])
        s = 'interrupt input' if (cmd[0] & 0x04) else 'VDI output'
        self.putx(0, 1, ['pin16 = ' + s])
        VDI_NAMES = ['Fast', 'Medium', 'Slow', 'Always on']
        vdi_speed = VDI_NAMES[cmd[0] & 0x3]
        self.putx(0, 2, ['VDI: %s' % vdi_speed])
        BANDWIDTH_NAMES = ['Reserved', '400kHz', '340kHz', '270kHz', '200kHz',
                           '134kHz', '67kHz', 'Reserved']
        bandwidth = BANDWIDTH_NAMES[(cmd[1] & 0xE0) >> 5]
        self.putx(0, 3, ['Bandwidth: %s' % bandwidth])
        LNA_GAIN_NAMES = [0, -6, -14, -20]
        lna_gain = LNA_GAIN_NAMES[(cmd[1] & 0x18) >> 3]
        self.putx(0, 2, ['LNA gain: %ddB' % lna_gain])
        RSSI_THRESHOLD_NAMES = ['-103', '-97', '-91', '-85', '-79', '-73',
                                'Reserved', 'Reserved']
        rssi_threshold = RSSI_THRESHOLD_NAMES[cmd[1] & 0x7]
        self.putx(0, 3, ['RSSI threshold: %s' % rssi_threshold])

    def handle_data_filter_cmd(self, cmd, ret):
        self.putx(0, 8, ['Data filter command'])
        if cmd[1] & 0x80:
            clock_recovery = 'auto'
        elif cmd[1] & 0x40:
            clock_recovery = 'fast'
        else:
            clock_recovery = 'slow'
        self.putx(0, 2, ['Clock recovery: %s mode' % clock_recovery])
        self.advance_ann(0, 1) # Should always be 1.
        s = 'analog' if (cmd[1] & 0x10) else 'digital'
        self.putx(0, 1, ['Data filter: ' + s])
        self.advance_ann(0, 1) # Should always be 1.
        self.putx(0, 3, ['DQD threshold: %d' % (cmd[1] & 0x7)])

    def handle_fifo_and_reset_cmd(self, cmd, ret):
        self.putx(0, 8, ['FIFO and reset command'])
        fifo_level = (cmd[1] & 0xF0) >> 4
        self.putx(0, 4, ['FIFO trigger level: %d' % fifo_level])
        last_fifo_level = (self.last_fifo_and_reset & 0xF0) >> 4
        if fifo_level != last_fifo_level:
            self.putx(5, 4, ['Changing', '~'])
        else:
            self.advance_ann(5, 4)
        s = 'one byte' if (cmd[1] & 0x08) else 'two bytes'
        self.putx(0, 1, ['Synchron length: ' + s])
        if (cmd[1] & 0x08) != (self.last_fifo_and_reset & 0x08):
            self.putx(5, 1, ['Changing', '~'])
        else:
            self.advance_ann(5, 1)

        if cmd[1] & 0x04:
            fifo_fill = 'Always'
        elif cmd[1] & 0x02:
            fifo_fill = 'After synchron pattern'
        else:
            fifo_fill = 'Never'
        self.putx(0, 2, ['FIFO fill: %s' % fifo_fill])
        if (cmd[1] & 0x06) != (self.last_fifo_and_reset & 0x06):
            self.putx(5, 2, ['Changing', '~'])
        else:
            self.advance_ann(5, 2)

        s = 'non-sensitive' if (cmd[1] & 0x01) else 'sensitive'
        self.putx(0, 1, ['Reset mode: ' + s])
        if (cmd[1] & 0x01) != (self.last_fifo_and_reset & 0x01):
            self.putx(5, 1, ['Changing', '~'])
        else:
            self.advance_ann(5, 1)

        self.last_fifo_and_reset = cmd[1]

    def handle_synchron_pattern_cmd(self, cmd, ret):
        self.putx(0, 8, ['Synchron pattern command'])
        if self.last_fifo_and_reset & 0x08:
            self.putx(0, 8, ['Pattern: 0x2D%02X' % pattern])
        else:
            self.putx(0, 8, ['Pattern: %02X' % pattern])

    def handle_fifo_read_cmd(self, cmd, ret):
        self.putx(0, 8, ['FIFO read command', 'FIFO read'])
        self.putx(3, 8, ['Data: %02X' % ret[1]])

    def handle_afc_cmd(self, cmd, ret):
        self.putx(0, 8, ['AFC command'])
        MODES = ['Off', 'Once', 'During receiving', 'Always']
        mode = (cmd[1] & 0xC0) >> 6
        self.putx(0, 2, ['Mode: %s' % MODES[mode]])
        if (cmd[1] & 0xC0) != (self.last_afc & 0xC0):
            self.putx(5, 2, ['Changing', '~'])
        else:
            self.advance_ann(5, 2)

        range_limit = (cmd[1] & 0x30) >> 4
        FREQ_TABLE = [0.0, 2.5, 5.0, 7.5]
        freq_delta = FREQ_TABLE[(self.last_config & 0x30) >> 4]

        if range_limit == 0:
            self.putx(0, 2, ['Range: No limit'])
        elif range_limit == 1:
            self.putx(0, 2, ['Range: +/-%dkHz' % (15 * freq_delta)])
        elif range_limit == 2:
            self.putx(0, 2, ['Range: +/-%dkHz' % (7 * freq_delta)])
        elif range_limit == 3:
            self.putx(0, 2, ['Range: +/-%dkHz' % (3 * freq_delta)])

        if (cmd[1] & 0x30) != (self.last_afc & 0x30):
            self.putx(5, 2, ['Changing', '~'])
        else:
            self.advance_ann(5, 2)

        NAMES = ['Strobe edge', 'High accuracy mode', 'Enable offset register',
                 'Enable offset calculation']
        self.describe_bits(cmd[1] & 0xF, NAMES)
        self.describe_changed_bits(cmd[1] & 0xF, self.last_afc & 0xF, NAMES)

        self.last_afc = cmd[1]

    def handle_transceiver_control_cmd(self, cmd, ret):
        self.putx(0, 8, ['Transceiver control command'])
        self.putx(0, 4, ['FSK frequency delta: %dkHz' % (15 * ((cmd[1] & 0xF0) >> 4))])
        if cmd[1] & 0xF0 != self.last_transceiver & 0xF0:
            self.putx(5, 4, ['Changing', '~'])
        else:
            self.advance_ann(5, 4)

        POWERS = [0, -2.5, -5, -7.5, -10, -12.5, -15, -17.5]
        self.advance_ann(0, 1)
        self.advance_ann(5, 1)
        self.putx(0,3, ['Relative power: %dB' % (cmd[1] & 0x07)])
        if (cmd[1] & 0x07) != (self.last_transceiver & 0x07):
            self.putx(5, 3, ['Changing', '~'])
        else:
            self.advance_ann(5, 3)
        self.last_transceiver = cmd[1]

    def handle_pll_setting_cmd(self, cmd, ret):
        self.putx(0, 8, ['PLL setting command'])
        self.advance_ann(0, 1)
        self.putx(0, 2, ['Clock buffer rise and fall time'])
        self.advance_ann(0, 1)
        self.advance_ann(5, 4)
        NAMES = [['Delay in phase detector', 'dly'], ['Disable dithering', 'ddit']]
        self.describe_bits((cmd[1] & 0xC) >> 2, NAMES)
        self.describe_changed_bits((cmd[1] & 0xC) >> 2, (self.last_pll & 0xC) >> 2, NAMES)
        s = '256kbps, high' if (cmd[1] & 0x01) else '86.2kbps, low'
        self.putx(0, 1, ['Max bit rate: %s noise' % s])

        self.advance_ann(5, 1)
        if (cmd[1] & 0x01) != (self.last_pll & 0x01):
            self.putx(5, 1, ['Changing', '~'])

        self.last_pll = cmd[1]

    def handle_transmitter_register_cmd(self, cmd, ret):
        self.putx(0, 8, ['Transmitter register command', 'Transmit'])
        self.putx(0, 8, ['Data: %s' % cmd[1], '%s' % cmd[1]])

    def handle_software_reset_cmd(self, cmd, ret):
        self.putx(0, 16, ['Software reset command'])

    def handle_wake_up_timer_cmd(self, cmd, ret):
        self.putx(0, 3, ['Wake-up timer command', 'Timer'])
        r = cmd[0] & 0x1F
        m = cmd[1]
        time = 1.03 * m * pow(2, r) + 0.5
        self.putx(0, 13, ['Time: %7.2f' % time])

    def handle_low_duty_cycle_cmd(self, cmd, ret):
        self.putx(0, 16, ['Low duty cycle command'])

    def handle_low_battery_detector_cmd(self, cmd, ret):
        self.putx(0, 8, ['Low battery detector command'])
        NAMES = ['1', '1.25', '1.66', '2', '2.5', '3.33', '5', '10']
        clock = NAMES[(cmd[1] & 0xE0) >> 5]
        self.putx(0, 3, ['Clock output: %sMHz' % clock, '%sMHz' % clock])
        self.advance_ann(0, 1)
        v = 2.25 + (cmd[1] & 0x0F) * 0.1
        self.putx(0, 4, ['Low battery voltage: %1.2fV' % v, '%1.2fV' % v])

    def handle_status_read_cmd(self, cmd, ret):
        self.putx(0, 8, ['Status read command', 'Status'])
        NAMES = ['RGIT/FFIT', 'POR', 'RGUR/FFOV', 'WKUP', 'EXT', 'LBD',
                 'FFEM', 'RSSI/ATS', 'DQD', 'CRL', 'ATGL']
        status = (ret[0] << 3) + (ret[1] >> 5)
        self.row_pos[1] -= 8
        self.row_pos[2] -= 8
        self.describe_return_bits(status, NAMES)
        receiver_enabled = (self.last_power & 0x80) >> 7

        if ret[0] & 0x80:
            if receiver_enabled:
                s = 'Received data in FIFO'
            else:
                s = 'Transmit register ready'
            self.putx(5, 1, s)
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x40:
            self.putx(5, 1, 'Power on Reset')
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x20:
            if receiver_enabled:
                s = 'RX FIFO overflow'
            else:
                s = 'Transmit register under run'
            self.putx(5, 1, s)
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x10:
            self.putx(5, 1, 'Wake-up timer')
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x08:
            self.putx(5, 1, 'External interrupt')
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x04:
            self.putx(5, 1, 'Low battery')
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x02:
            self.putx(5, 1, 'FIFO is empty')
        else:
            self.advance_ann(5, 1)
        if ret[0] & 0x01:
            if receiver_enabled:
                s = 'Incoming signal above limit'
            else:
                s = 'Antenna detected RF signal'
            self.putx(5, 1, s)
        else:
            self.advance_ann(5, 1)
        if ret[1] & 0x80:
            self.putx(5, 1, 'Data quality detector')
        else:
            self.advance_ann(5, 1)
        if ret[1] & 0x40:
            self.putx(5, 1, 'Clock recovery locked')
        else:
            self.advance_ann(5, 1)
        self.advance_ann(5, 1)

        self.putx(3, 5, ['AFC offset'])
        if (self.last_status[1] & 0x1F) != (ret[1] & 0x1F):
            self.putx(5, 5, ['Changed', '~'])
        self.last_status = ret

    def handle_cmd(self, cmd, ret):
        if cmd[0] == 0x80:
            self.handle_configuration_cmd(cmd, ret)
        elif cmd[0] == 0x82:
            self.handle_power_management_cmd(cmd, ret)
        elif cmd[0] & 0xF0 == 0xA0:
            self.handle_frequency_setting_cmd(cmd, ret)
        elif cmd[0] == 0xC6:
            self.handle_data_rate_cmd(cmd, ret)
        elif cmd[0] & 0xF8 == 0x90:
            self.handle_receiver_control_cmd(cmd, ret)
        elif cmd[0] == 0xC2:
            self.handle_data_filter_cmd(cmd, ret)
        elif cmd[0] == 0xCA:
            self.handle_fifo_and_reset_cmd(cmd, ret)
        elif cmd[0] == 0xCE:
            self.handle_synchron_pattern_cmd(cmd, ret)
        elif cmd[0] == 0xB0:
            self.handle_fifo_read_cmd(cmd, ret)
        elif cmd[0] == 0xC4:
            self.handle_afc_cmd(cmd, ret)
        elif cmd[0] & 0xFE == 0x98:
            self.handle_transceiver_control_cmd(cmd, ret)
        elif cmd[0] == 0xCC:
            self.handle_pll_setting_cmd(cmd, ret)
        elif cmd[0] == 0xB8:
            self.handle_transmitter_register_cmd(cmd, ret)
        elif cmd[0] == 0xFE:
            self.handle_software_reset_cmd(cmd, ret)
        elif cmd[0] & 0xE0 == 0xE0:
            self.handle_wake_up_timer_cmd(cmd, ret)
        elif cmd[0] == 0xC8:
            self.handle_low_duty_cycle_cmd(cmd, ret)
        elif cmd[0] == 0xC0:
            self.handle_low_battery_detector_cmd(cmd, ret)
        elif cmd[0] == 0x00:
            self.handle_status_read_cmd(cmd, ret)
        else:
            c = '%02x %02x' % tuple(cmd)
            r = '%02x %02x' % tuple(ret)
            self.putx(0, 16, ['Unknown command: %s (reply: %s)!' % (c, r)])

    def decode(self, ss, es, data):
        ptype, mosi, miso = data

        # For now, only use DATA and BITS packets.
        if ptype not in ('DATA', 'BITS'):
            return

        # Store the individual bit values and ss/es numbers. The next packet
        # is guaranteed to be a 'DATA' packet belonging to this 'BITS' one.
        if ptype == 'BITS':
            if mosi is not None:
                self.mosi_bits.extend(reversed(mosi))
            if miso is not None:
                self.miso_bits.extend(reversed(miso))
            return

        # Append new bytes.
        self.mosi_bytes.append(mosi)
        self.miso_bytes.append(miso)

        # All commands consist of 2 bytes.
        if len(self.mosi_bytes) < 2:
            return

        self.row_pos = [0, 8, 8]

        self.handle_cmd(self.mosi_bytes, self.miso_bytes)

        self.mosi_bytes, self.miso_bytes = [], []
        self.mosi_bits, self.miso_bits = [], []
Commit	Line	Data
d44c802b SP	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
cac173db	4	## Copyright (C) 2014 Sławek Piotrowski <sentinel@atteo.org>
d44c802b SP	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
4539e9ca	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
d44c802b SP	18	##
d44c802b SP	19
d44c802b SP	20	import sigrokdecode as srd
	21
	22	class Decoder(srd.Decoder):
b197383c	23	api_version = 3
d44c802b SP	24	id = 'rfm12'
	25	name = 'RFM12'
	26	longname = 'RFM12 control protocol'
cac173db	27	desc = 'HopeRF RFM12 wireless transceiver control protocol.'
d44c802b SP	28	license = 'gplv2+'
	29	inputs = ['spi']
	30	outputs = ['rfm12']
d6d8a8a4	31	tags = ['Wireless/RF']
d44c802b SP	32	annotations = (
	33	('cmd', 'Command'),
	34	('params', 'Command parameters'),
	35	('disabled', 'Disabled bits'),
	36	('return', 'Returned values'),
	37	('disabled_return', 'Disabled returned values'),
	38	('interpretation', 'Interpretation'),
	39	)
	40	annotation_rows = (
	41	('commands', 'Commands', (0, 1, 2)),
	42	('return', 'Return', (3, 4)),
	43	('interpretation', 'Interpretation', (5,)),
	44	)
	45
92b7b49f	46	def __init__(self):
10aeb8ea GS	47	self.reset()
	48
	49	def reset(self):
d44c802b SP	50	self.mosi_bytes, self.miso_bytes = [], []
	51	self.mosi_bits, self.miso_bits = [], []
	52	self.row_pos = [0, 0, 0]
	53
	54	self.ann_to_row = [0, 0, 0, 1, 1, 2]
	55
	56	# Initialize with Power-On-Reset values.
	57	self.last_status = [0x00, 0x00]
	58	self.last_config = 0x08
	59	self.last_power = 0x08
	60	self.last_freq = 0x680
	61	self.last_data_rate = 0x23
	62	self.last_fifo_and_reset = 0x80
	63	self.last_afc = 0xF7
	64	self.last_transceiver = 0x00
	65	self.last_pll = 0x77
	66
	67	def advance_ann(self, ann, length):
	68	row = self.ann_to_row[ann]
	69	self.row_pos[row] += length
	70
	71	def putx(self, ann, length, description):
	72	if not isinstance(description, list):
	73	description = [description]
	74	row = self.ann_to_row[ann]
	75	bit = self.row_pos[row]
	76	self.put(self.mosi_bits[bit][1], self.mosi_bits[bit + length - 1][2],
	77	self.out_ann, [ann, description])
	78	bit += length
	79	self.row_pos[row] = bit
	80
	81	def describe_bits(self, data, names):
	82	i = 0x01 << len(names) - 1
	83	bit = 0
	84	while i != 0:
	85	if names[bit] != '':
	86	self.putx(1 if (data & i) else 2, 1, names[bit])
	87	i >>= 1
	88	bit += 1
	89
	90	def describe_return_bits(self, data, names):
	91	i = 0x01 << len(names) - 1
	92	bit = 0
	93	while i != 0:
	94	if names[bit] != '':
	95	self.putx(3 if (data & i) else 4, 1, names[bit])
	96	else:
	97	self.advance_ann(3, 1)
	98	i >>= 1
	99	bit += 1
	100
	101	def describe_changed_bits(self, data, old_data, names):
	102	changes = data ^ old_data
	103	i = 0x01 << (len(names) - 1)
	104	bit = 0
	105	while i != 0:
	106	if names[bit] != '' and changes & i:
	107	s = ['+', 'Turning on'] if (data & i) else ['-', 'Turning off']
	108	self.putx(5, 1, s)
	109	else:
	110	self.advance_ann(5, 1)
	111	i >>= 1
	112	bit += 1
	113
114	def start(self):
115	self.out_ann = self.register(srd.OUTPUT_ANN)
116
117	def handle_configuration_cmd(self, cmd, ret):
118	self.putx(0, 8, ['Configuration command', 'Configuration'])
119	NAMES = [['Internal data register', 'el'], ['FIFO mode', 'ef']]
120
121	bits = (cmd[1] & 0xC0) >> 6
122	old_bits = (self.last_config & 0xC0) >> 6
123	self.describe_bits(bits, NAMES)
124	self.describe_changed_bits(bits, old_bits, NAMES)
125
c9021bc9	126	FREQUENCIES = ['315', '433', '868', '915']
d44c802b SP	127	f = FREQUENCIES[(cmd[1] & 0x30) >> 4] + 'MHz'
	128	self.putx(1, 2, ['Frequency: ' + f, f])
	129	if cmd[1] & 0x30 != self.last_config & 0x30:
	130	self.putx(5, 2, ['Changed', '~'])
	131
	132	c = '%.1fpF' % (8.5 + (cmd[1] & 0xF) * 0.5)
	133	self.putx(1, 4, ['Capacitance: ' + c, c])
	134	if cmd[1] & 0xF != self.last_config & 0xF:
	135	self.putx(5, 4, ['Changed', '~'])
	136
	137	self.last_config = cmd[1]
	138
	139	def handle_power_management_cmd(self, cmd, ret):
	140	self.putx(0, 8, ['Power management', 'Power'])
	141	NAMES = [['Receiver chain', 'er'], ['Baseband circuit', 'ebb'],
	142	['Transmission', 'et'], ['Synthesizer', 'es'],
	143	['Crystal oscillator', 'ex'], ['Low battery detector', 'eb'],
	144	['Wake-up timer', 'ew'], ['Clock output off switch', 'dc']]
	145
	146	self.describe_bits(cmd[1], NAMES)
	147
	148	power = cmd[1]
	149
	150	# Some bits imply other, even if they are set to 0.
	151	if power & 0x80:
	152	power \|= 0x58
	153	if power & 0x20:
	154	power \|= 0x18
	155	self.describe_changed_bits(power, self.last_power, NAMES)
	156
	157	self.last_power = power
	158
	159	def handle_frequency_setting_cmd(self, cmd, ret):
	160	self.putx(0, 4, ['Frequency setting', 'Frequency'])
	161	f = ((cmd[1] & 0xF) << 8) + cmd[2]
	162	self.putx(0, 12, ['F = %3.4f' % f])
	163	self.row_pos[2] -= 4
	164	if self.last_freq != f:
	165	self.putx(5, 12, ['Changing', '~'])
	166	self.last_freq = f
	167
	168	def handle_data_rate_cmd(self, cmd, ret):
	169	self.putx(0, 8, ['Data rate command', 'Data rate'])
	170	r = cmd[1] & 0x7F
	171	cs = (cmd[1] & 0x80) >> 7
	172	rate = 10000 / 29.0 / (r + 1) / (1 + 7 * cs)
	173	self.putx(0, 8, ['%3.1fkbps' % rate])
	174	if self.last_data_rate != cmd[1]:
	175	self.putx(5, 8, ['Changing', '~'])
	176	self.last_data_rate = cmd[1]
	177
	178	def handle_receiver_control_cmd(self, cmd, ret):
	179	self.putx(0, 5, ['Receiver control command'])
	180	s = 'interrupt input' if (cmd[0] & 0x04) else 'VDI output'
	181	self.putx(0, 1, ['pin16 = ' + s])
	182	VDI_NAMES = ['Fast', 'Medium', 'Slow', 'Always on']
	183	vdi_speed = VDI_NAMES[cmd[0] & 0x3]
	184	self.putx(0, 2, ['VDI: %s' % vdi_speed])
	185	BANDWIDTH_NAMES = ['Reserved', '400kHz', '340kHz', '270kHz', '200kHz',
	186	'134kHz', '67kHz', 'Reserved']
	187	bandwidth = BANDWIDTH_NAMES[(cmd[1] & 0xE0) >> 5]
	188	self.putx(0, 3, ['Bandwidth: %s' % bandwidth])
	189	LNA_GAIN_NAMES = [0, -6, -14, -20]
	190	lna_gain = LNA_GAIN_NAMES[(cmd[1] & 0x18) >> 3]
191	self.putx(0, 2, ['LNA gain: %ddB' % lna_gain])
192	RSSI_THRESHOLD_NAMES = ['-103', '-97', '-91', '-85', '-79', '-73',
193	'Reserved', 'Reserved']
194	rssi_threshold = RSSI_THRESHOLD_NAMES[cmd[1] & 0x7]
195	self.putx(0, 3, ['RSSI threshold: %s' % rssi_threshold])
196
197	def handle_data_filter_cmd(self, cmd, ret):
198	self.putx(0, 8, ['Data filter command'])
199	if cmd[1] & 0x80:
200	clock_recovery = 'auto'
201	elif cmd[1] & 0x40:
202	clock_recovery = 'fast'
203	else:
204	clock_recovery = 'slow'
205	self.putx(0, 2, ['Clock recovery: %s mode' % clock_recovery])
206	self.advance_ann(0, 1) # Should always be 1.
207	s = 'analog' if (cmd[1] & 0x10) else 'digital'
208	self.putx(0, 1, ['Data filter: ' + s])
209	self.advance_ann(0, 1) # Should always be 1.
210	self.putx(0, 3, ['DQD threshold: %d' % (cmd[1] & 0x7)])
211
212	def handle_fifo_and_reset_cmd(self, cmd, ret):
213	self.putx(0, 8, ['FIFO and reset command'])
214	fifo_level = (cmd[1] & 0xF0) >> 4
215	self.putx(0, 4, ['FIFO trigger level: %d' % fifo_level])
216	last_fifo_level = (self.last_fifo_and_reset & 0xF0) >> 4
217	if fifo_level != last_fifo_level:
218	self.putx(5, 4, ['Changing', '~'])
219	else:
220	self.advance_ann(5, 4)
221	s = 'one byte' if (cmd[1] & 0x08) else 'two bytes'
222	self.putx(0, 1, ['Synchron length: ' + s])
223	if (cmd[1] & 0x08) != (self.last_fifo_and_reset & 0x08):
224	self.putx(5, 1, ['Changing', '~'])
225	else:
226	self.advance_ann(5, 1)
227
228	if cmd[1] & 0x04:
229	fifo_fill = 'Always'
230	elif cmd[1] & 0x02:
231	fifo_fill = 'After synchron pattern'
232	else:
233	fifo_fill = 'Never'
234	self.putx(0, 2, ['FIFO fill: %s' % fifo_fill])
235	if (cmd[1] & 0x06) != (self.last_fifo_and_reset & 0x06):
236	self.putx(5, 2, ['Changing', '~'])
237	else:
238	self.advance_ann(5, 2)
239
240	s = 'non-sensitive' if (cmd[1] & 0x01) else 'sensitive'
241	self.putx(0, 1, ['Reset mode: ' + s])
242	if (cmd[1] & 0x01) != (self.last_fifo_and_reset & 0x01):
243	self.putx(5, 1, ['Changing', '~'])
244	else:
245	self.advance_ann(5, 1)
246
247	self.last_fifo_and_reset = cmd[1]
248
249	def handle_synchron_pattern_cmd(self, cmd, ret):
250	self.putx(0, 8, ['Synchron pattern command'])
251	if self.last_fifo_and_reset & 0x08:
252	self.putx(0, 8, ['Pattern: 0x2D%02X' % pattern])
253	else:
254	self.putx(0, 8, ['Pattern: %02X' % pattern])
255
256	def handle_fifo_read_cmd(self, cmd, ret):
257	self.putx(0, 8, ['FIFO read command', 'FIFO read'])
258	self.putx(3, 8, ['Data: %02X' % ret[1]])
259
260	def handle_afc_cmd(self, cmd, ret):
261	self.putx(0, 8, ['AFC command'])
262	MODES = ['Off', 'Once', 'During receiving', 'Always']
263	mode = (cmd[1] & 0xC0) >> 6
264	self.putx(0, 2, ['Mode: %s' % MODES[mode]])
265	if (cmd[1] & 0xC0) != (self.last_afc & 0xC0):
266	self.putx(5, 2, ['Changing', '~'])
267	else:
268	self.advance_ann(5, 2)
269
04ff4926	270	range_limit = (cmd[1] & 0x30) >> 4
d44c802b SP	271	FREQ_TABLE = [0.0, 2.5, 5.0, 7.5]
	272	freq_delta = FREQ_TABLE[(self.last_config & 0x30) >> 4]
	273
04ff4926	274	if range_limit == 0:
d44c802b	275	self.putx(0, 2, ['Range: No limit'])
04ff4926	276	elif range_limit == 1:
d44c802b	277	self.putx(0, 2, ['Range: +/-%dkHz' % (15 * freq_delta)])
04ff4926	278	elif range_limit == 2:
d44c802b	279	self.putx(0, 2, ['Range: +/-%dkHz' % (7 * freq_delta)])
04ff4926	280	elif range_limit == 3:
d44c802b SP	281	self.putx(0, 2, ['Range: +/-%dkHz' % (3 * freq_delta)])
	282
	283	if (cmd[1] & 0x30) != (self.last_afc & 0x30):
	284	self.putx(5, 2, ['Changing', '~'])
	285	else:
	286	self.advance_ann(5, 2)
	287
	288	NAMES = ['Strobe edge', 'High accuracy mode', 'Enable offset register',
	289	'Enable offset calculation']
	290	self.describe_bits(cmd[1] & 0xF, NAMES)
	291	self.describe_changed_bits(cmd[1] & 0xF, self.last_afc & 0xF, NAMES)
	292
	293	self.last_afc = cmd[1]
	294
	295	def handle_transceiver_control_cmd(self, cmd, ret):
	296	self.putx(0, 8, ['Transceiver control command'])
	297	self.putx(0, 4, ['FSK frequency delta: %dkHz' % (15 * ((cmd[1] & 0xF0) >> 4))])
	298	if cmd[1] & 0xF0 != self.last_transceiver & 0xF0:
	299	self.putx(5, 4, ['Changing', '~'])
	300	else:
	301	self.advance_ann(5, 4)
	302
	303	POWERS = [0, -2.5, -5, -7.5, -10, -12.5, -15, -17.5]
	304	self.advance_ann(0, 1)
	305	self.advance_ann(5, 1)
	306	self.putx(0,3, ['Relative power: %dB' % (cmd[1] & 0x07)])
	307	if (cmd[1] & 0x07) != (self.last_transceiver & 0x07):
	308	self.putx(5, 3, ['Changing', '~'])
	309	else:
	310	self.advance_ann(5, 3)
	311	self.last_transceiver = cmd[1]
	312
	313	def handle_pll_setting_cmd(self, cmd, ret):
	314	self.putx(0, 8, ['PLL setting command'])
	315	self.advance_ann(0, 1)
	316	self.putx(0, 2, ['Clock buffer rise and fall time'])
	317	self.advance_ann(0, 1)
	318	self.advance_ann(5, 4)
	319	NAMES = [['Delay in phase detector', 'dly'], ['Disable dithering', 'ddit']]
	320	self.describe_bits((cmd[1] & 0xC) >> 2, NAMES)
	321	self.describe_changed_bits((cmd[1] & 0xC) >> 2, (self.last_pll & 0xC) >> 2, NAMES)
	322	s = '256kbps, high' if (cmd[1] & 0x01) else '86.2kbps, low'
	323	self.putx(0, 1, ['Max bit rate: %s noise' % s])
	324
	325	self.advance_ann(5, 1)
	326	if (cmd[1] & 0x01) != (self.last_pll & 0x01):
	327	self.putx(5, 1, ['Changing', '~'])
	328
	329	self.last_pll = cmd[1]
	330
	331	def handle_transmitter_register_cmd(self, cmd, ret):
	332	self.putx(0, 8, ['Transmitter register command', 'Transmit'])
	333	self.putx(0, 8, ['Data: %s' % cmd[1], '%s' % cmd[1]])
	334
	335	def handle_software_reset_cmd(self, cmd, ret):
	336	self.putx(0, 16, ['Software reset command'])
	337
	338	def handle_wake_up_timer_cmd(self, cmd, ret):
	339	self.putx(0, 3, ['Wake-up timer command', 'Timer'])
	340	r = cmd[0] & 0x1F
	341	m = cmd[1]
	342	time = 1.03 * m * pow(2, r) + 0.5
	343	self.putx(0, 13, ['Time: %7.2f' % time])
	344
345	def handle_low_duty_cycle_cmd(self, cmd, ret):
346	self.putx(0, 16, ['Low duty cycle command'])
347
348	def handle_low_battery_detector_cmd(self, cmd, ret):
349	self.putx(0, 8, ['Low battery detector command'])
350	NAMES = ['1', '1.25', '1.66', '2', '2.5', '3.33', '5', '10']
351	clock = NAMES[(cmd[1] & 0xE0) >> 5]
352	self.putx(0, 3, ['Clock output: %sMHz' % clock, '%sMHz' % clock])
353	self.advance_ann(0, 1)
354	v = 2.25 + (cmd[1] & 0x0F) * 0.1
355	self.putx(0, 4, ['Low battery voltage: %1.2fV' % v, '%1.2fV' % v])
356
357	def handle_status_read_cmd(self, cmd, ret):
358	self.putx(0, 8, ['Status read command', 'Status'])
359	NAMES = ['RGIT/FFIT', 'POR', 'RGUR/FFOV', 'WKUP', 'EXT', 'LBD',
360	'FFEM', 'RSSI/ATS', 'DQD', 'CRL', 'ATGL']
361	status = (ret[0] << 3) + (ret[1] >> 5)
362	self.row_pos[1] -= 8
363	self.row_pos[2] -= 8
364	self.describe_return_bits(status, NAMES)
365	receiver_enabled = (self.last_power & 0x80) >> 7
366
367	if ret[0] & 0x80:
368	if receiver_enabled:
369	s = 'Received data in FIFO'
370	else:
371	s = 'Transmit register ready'
372	self.putx(5, 1, s)
373	else:
374	self.advance_ann(5, 1)
375	if ret[0] & 0x40:
376	self.putx(5, 1, 'Power on Reset')
377	else:
378	self.advance_ann(5, 1)
379	if ret[0] & 0x20:
380	if receiver_enabled:
381	s = 'RX FIFO overflow'
382	else:
383	s = 'Transmit register under run'
384	self.putx(5, 1, s)
385	else:
386	self.advance_ann(5, 1)
387	if ret[0] & 0x10:
388	self.putx(5, 1, 'Wake-up timer')
389	else:
390	self.advance_ann(5, 1)
391	if ret[0] & 0x08:
392	self.putx(5, 1, 'External interrupt')
393	else:
394	self.advance_ann(5, 1)
395	if ret[0] & 0x04:
396	self.putx(5, 1, 'Low battery')
397	else:
398	self.advance_ann(5, 1)
399	if ret[0] & 0x02:
400	self.putx(5, 1, 'FIFO is empty')
401	else:
402	self.advance_ann(5, 1)
403	if ret[0] & 0x01:
404	if receiver_enabled:
405	s = 'Incoming signal above limit'
406	else:
407	s = 'Antenna detected RF signal'
408	self.putx(5, 1, s)
409	else:
410	self.advance_ann(5, 1)
411	if ret[1] & 0x80:
412	self.putx(5, 1, 'Data quality detector')
413	else:
414	self.advance_ann(5, 1)
415	if ret[1] & 0x40:
416	self.putx(5, 1, 'Clock recovery locked')
417	else:
418	self.advance_ann(5, 1)
419	self.advance_ann(5, 1)
420
421	self.putx(3, 5, ['AFC offset'])
422	if (self.last_status[1] & 0x1F) != (ret[1] & 0x1F):
423	self.putx(5, 5, ['Changed', '~'])
424	self.last_status = ret
425
426	def handle_cmd(self, cmd, ret):
427	if cmd[0] == 0x80:
428	self.handle_configuration_cmd(cmd, ret)
429	elif cmd[0] == 0x82:
430	self.handle_power_management_cmd(cmd, ret)
431	elif cmd[0] & 0xF0 == 0xA0:
432	self.handle_frequency_setting_cmd(cmd, ret)
433	elif cmd[0] == 0xC6:
434	self.handle_data_rate_cmd(cmd, ret)
435	elif cmd[0] & 0xF8 == 0x90:
436	self.handle_receiver_control_cmd(cmd, ret)
437	elif cmd[0] == 0xC2:
438	self.handle_data_filter_cmd(cmd, ret)
439	elif cmd[0] == 0xCA:
440	self.handle_fifo_and_reset_cmd(cmd, ret)
441	elif cmd[0] == 0xCE:
442	self.handle_synchron_pattern_cmd(cmd, ret)
443	elif cmd[0] == 0xB0:
444	self.handle_fifo_read_cmd(cmd, ret)
445	elif cmd[0] == 0xC4:
446	self.handle_afc_cmd(cmd, ret)
447	elif cmd[0] & 0xFE == 0x98:
448	self.handle_transceiver_control_cmd(cmd, ret)
449	elif cmd[0] == 0xCC:
450	self.handle_pll_setting_cmd(cmd, ret)
451	elif cmd[0] == 0xB8:
452	self.handle_transmitter_register_cmd(cmd, ret)
453	elif cmd[0] == 0xFE:
454	self.handle_software_reset_cmd(cmd, ret)
455	elif cmd[0] & 0xE0 == 0xE0:
456	self.handle_wake_up_timer_cmd(cmd, ret)
457	elif cmd[0] == 0xC8:
458	self.handle_low_duty_cycle_cmd(cmd, ret)
459	elif cmd[0] == 0xC0:
460	self.handle_low_battery_detector_cmd(cmd, ret)
461	elif cmd[0] == 0x00:
462	self.handle_status_read_cmd(cmd, ret)
463	else:
464	c = '%02x %02x' % tuple(cmd)
465	r = '%02x %02x' % tuple(ret)
d9673085	466	self.putx(0, 16, ['Unknown command: %s (reply: %s)!' % (c, r)])
d44c802b SP	467
	468	def decode(self, ss, es, data):
	469	ptype, mosi, miso = data
	470
	471	# For now, only use DATA and BITS packets.
	472	if ptype not in ('DATA', 'BITS'):
	473	return
	474
	475	# Store the individual bit values and ss/es numbers. The next packet
	476	# is guaranteed to be a 'DATA' packet belonging to this 'BITS' one.
	477	if ptype == 'BITS':
	478	if mosi is not None:
	479	self.mosi_bits.extend(reversed(mosi))
	480	if miso is not None:
	481	self.miso_bits.extend(reversed(miso))
	482	return
	483
	484	# Append new bytes.
	485	self.mosi_bytes.append(mosi)
	486	self.miso_bytes.append(miso)
	487
	488	# All commands consist of 2 bytes.
	489	if len(self.mosi_bytes) < 2:
	490	return
	491
	492	self.row_pos = [0, 8, 8]
	493
4ef0ff31	494	self.handle_cmd(self.mosi_bytes, self.miso_bytes)
d44c802b SP	495
	496	self.mosi_bytes, self.miso_bytes = [], []
	497	self.mosi_bits, self.miso_bits = [], []