]>
Commit | Line | Data |
---|---|---|
b4332f0f UH |
1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2014 Torsten Duwe <duwe@suse.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | class Decoder(srd.Decoder): | |
24 | api_version = 2 | |
25 | id = 'pwm' | |
26 | name = 'PWM' | |
27 | longname = 'Pulse-width modulation' | |
28 | desc = 'Analog level encoded in duty cycle percentage.' | |
29 | license = 'gplv2+' | |
30 | inputs = ['logic'] | |
31 | outputs = ['pwm'] | |
32 | channels = ( | |
33 | {'id': 'pwm', 'name': 'PWM in', 'desc': 'Modulation pulses'}, | |
34 | ) | |
35 | options = ( | |
36 | {'id': 'new_cycle_edge', 'desc': 'New cycle on which edge', | |
37 | 'default': 'rising', 'values': ('rising', 'falling')}, | |
38 | ) | |
39 | annotations = ( | |
40 | ('value', 'PWM value'), | |
41 | ) | |
42 | binary = ( | |
43 | ('raw', 'RAW file'), | |
44 | ) | |
45 | ||
46 | def __init__(self, **kwargs): | |
47 | self.ss = self.es = -1 | |
48 | self.high = 1 | |
49 | self.low = 1 | |
50 | self.lastedge = 0 | |
51 | self.oldpin = 0 | |
52 | self.startedge = 0 | |
53 | self.num_cycles = 0 | |
54 | ||
55 | def start(self): | |
56 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
57 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
58 | self.out_bin = self.register(srd.OUTPUT_BINARY) | |
59 | self.out_freq = self.register(srd.OUTPUT_META, | |
60 | meta=(int, 'Frequency', 'PWM base (cycle) frequency')) | |
61 | self.startedge = 0 | |
62 | if self.options['new_cycle_edge'] == 'falling': | |
63 | self.startedge = 1 | |
64 | ||
65 | def putx(self, data): | |
66 | self.put(self.ss, self.es, self.out_ann, data) | |
67 | ||
68 | def putp(self, data): | |
69 | self.put(self.ss, self.es, self.out_python, data) | |
70 | ||
71 | def putb(self, data): | |
72 | self.put(self.num_cycles, self.num_cycles, self.out_bin, data) | |
73 | ||
74 | def decode(self, ss, es, data): | |
75 | for (self.samplenum, pins) in data: | |
76 | # Ignore identical samples early on (for performance reasons). | |
77 | if self.oldpin == pins[0]: | |
78 | continue | |
79 | ||
80 | if self.oldpin == 0: # Rising edge. | |
81 | self.low = self.samplenum - self.lastedge | |
82 | else: | |
83 | self.high = self.samplenum - self.lastedge | |
84 | ||
85 | if self.oldpin == self.startedge: | |
86 | self.es = self.samplenum # This interval ends at this edge. | |
87 | if self.ss >= 0: # Have we completed a hi-lo sequence? | |
88 | self.putx([0, ["%d%%" % ((100 * self.high) // (self.high + self.low))]]) | |
89 | self.putb((0, bytes([(256 * self.high) // (self.high + self.low)]))) | |
90 | self.num_cycles += 1 | |
91 | else: | |
92 | # Mid-interval. | |
93 | # This interval started at the previous edge. | |
94 | self.ss = self.lastedge | |
95 | ||
96 | self.lastedge = self.samplenum | |
97 | self.oldpin = pins[0] |