]> sigrok.org Git - libsigrokdecode.git/blame - decoders/pca9571/pd.py
pca9571: Add initial OUTPUT_LOGIC support.
[libsigrokdecode.git] / decoders / pca9571 / pd.py
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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2019 Mickael Bosch <mickael.bosch@linux.com>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, see <http://www.gnu.org/licenses/>.
18##
19
20import sigrokdecode as srd
21
22NUM_OUTPUT_CHANNELS = 8
23
24# TODO: Other I²C functions: general call / reset address, device ID address.
25
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26def logic_channels(num_channels):
27 l = []
28 for i in range(num_channels):
29 l.append(tuple(['p%d' % i, 'P%d' % i, 100000]))
30 return tuple(l)
31
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32class Decoder(srd.Decoder):
33 api_version = 3
34 id = 'pca9571'
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35 name = 'PCA9571'
36 longname = 'NXP PCA9571'
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37 desc = 'NXP PCA9571 8-bit I²C output expander.'
38 license = 'gplv2+'
39 inputs = ['i2c']
40 outputs = []
41 tags = ['Embedded/industrial', 'IC']
42 annotations = (
43 ('register', 'Register type'),
44 ('value', 'Register value'),
e144452b 45 ('warning', 'Warning'),
70d258a5 46 )
f22b1c74 47 logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
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48 annotation_rows = (
49 ('regs', 'Registers', (0, 1)),
50 ('warnings', 'Warnings', (2,)),
51 )
52
53 def __init__(self):
54 self.reset()
55
56 def reset(self):
57 self.state = 'IDLE'
f22b1c74 58 self.ss_logic = -1
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59 self.last_write = 0xFF # Chip port default state is high.
60
61 def start(self):
62 self.out_ann = self.register(srd.OUTPUT_ANN)
f22b1c74 63 self.out_logic = self.register(srd.OUTPUT_LOGIC)
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64
65 def putx(self, data):
66 self.put(self.ss, self.es, self.out_ann, data)
67
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68 def putl(self, data):
69 self.put(self.ss_logic, self.ss_logic, self.out_logic, data)
70
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71 def handle_io(self, b):
72 if self.state == 'READ DATA':
73 operation = ['Outputs read', 'R']
74 if b != self.last_write:
75 self.putx([2, ['Warning: read value and last write value '
76 '(%02X) are different' % self.last_write]])
77 else:
78 operation = ['Outputs set', 'W']
79 self.last_write = b
80 self.putx([1, [operation[0] + ': %02X' % b,
81 operation[1] + ': %02X' % b]])
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82 self.ss_logic = self.ss
83 for i in range(NUM_OUTPUT_CHANNELS):
84 bit = (b & (1 << i)) != 0
85 self.putl([i, bytes([bit])])
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86
87 def check_correct_chip(self, addr):
88 if addr != 0x25:
89 self.putx([2, ['Warning: I²C slave 0x%02X not a PCA9571 '
90 'compatible chip.' % addr]])
91 return False
92 return True
93
94 def decode(self, ss, es, data):
95 cmd, databyte = data
96 self.ss, self.es = ss, es
97
98 # State machine.
99 if cmd in ('ACK', 'BITS'): # Discard 'ACK' and 'BITS'.
100 pass
101 elif cmd in ('START', 'START REPEAT'): # Start a communication.
102 self.state = 'GET SLAVE ADDR'
103 elif cmd in ('NACK', 'STOP'): # Reset the state machine.
104 self.state = 'IDLE'
105 elif cmd in ('ADDRESS READ', 'ADDRESS WRITE'):
106 if ((self.state == 'GET SLAVE ADDR') and
107 self.check_correct_chip(databyte)):
108 if cmd == 'ADDRESS READ':
109 self.state = 'READ DATA'
110 else:
111 self.state = 'WRITE DATA'
112 else:
113 self.state = 'IDLE'
114 elif cmd in ('DATA READ', 'DATA WRITE'):
115 if self.state in ('READ DATA', 'WRITE DATA'):
116 self.handle_io(databyte)
117 else:
118 self.state = 'IDLE'