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1##
2## This file is part of the sigrok project.
3##
4## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
21'''
e7720d6c 221-Wire protocol decoder (link layer).
51990c45 23
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24The 1-Wire protocol enables bidirectional communication over a single wire
25(and ground) between a single master and one or multiple slaves. The protocol
26is layered:
4633e258 27
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28 - Link layer (reset, presence detection, reading/writing bits)
29 - Network layer (skip/search/match device ROM addresses)
30 - Transport layer (transport data between 1-Wire master and device)
31
32Link layer protocol details:
a2b13347 33
f4d0363d 34Sample rate:
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35A sufficiently high samplerate is required to properly detect all the elements
36of the protocol. A lower samplerate can be used if the master does not use
37overdrive communication speed. The following minimal values should be used:
38
39 - overdrive available: 2MHz minimum, 5MHz suggested
40 - overdrive not available: 400kHz minimum, 1MHz suggested
f4d0363d 41
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42Probes:
431-Wire requires a single signal, but some master implementations might have a
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44separate signal used to deliver power to the bus during temperature conversion
45as an example. This power signal is currently not used.
46
47 - owr (1-Wire signal line)
48 - pwr (optional, dedicated power supply pin)
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49
50Options:
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511-Wire is an asynchronous protocol, so the decoder must know the samplerate.
52The timing for sampling bits, presence, and reset is calculated by the decoder,
a2b13347 53but in case the user wishes to use different values, it is possible to
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54configure the following timing values (number of samplerate periods):
55
56 - overdrive (if active the decoder will be prepared for overdrive)
57 - cnt_normal_bit (time for normal mode sample bit)
58 - cnt_normal_slot (time for normal mode data slot)
59 - cnt_normal_presence (time for normal mode sample presence)
60 - cnt_normal_reset (time for normal mode reset)
61 - cnt_overdrive_bit (time for overdrive mode sample bit)
62 - cnt_overdrive_slot (time for overdrive mode data slot)
63 - cnt_overdrive_presence (time for overdrive mode sample presence)
64 - cnt_overdrive_reset (time for overdrive mode reset)
65
66These options should be configured only on very rare cases and the user should
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67read the decoder source code to understand them correctly.
68
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69Protocol output format:
70TODO.
71
a2b13347 72Annotations:
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73
74Link layer annotations show the following events:
75
76 - NOTE/WARNING/ERROR
77 Possible samplerate related timing issues are reported.
78 - Reset/presence true/false
79 The event is marked from the signal negative edge to the end of the reset
80 high period. It's also reported if there are any devices attached to the bus.
81 - Bit 0/1
82 The event is marked from the signal negative edge to the end of the data
83 slot. The value of each received bit is also provided.
a2b13347 84
c08aea7e 85TODO:
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86- Check for protocol correctness, if events are timed inside prescribed limits.
87- Maybe add support for interrupts, check if this feature is deprecated.
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88'''
89
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90from .onewire_link import *
91