[libsigrokdecode.git] / decoders / onewire / onewire.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# 1-Wire protocol decoder

import sigrokdecode as srd

# Annotation feed formats
ANN_ASCII = 0
ANN_DEC = 1
ANN_HEX = 2
ANN_OCT = 3
ANN_BITS = 4

class Decoder(srd.Decoder):
    api_version = 1
    id = 'onewire'
    name = '1-Wire'
    longname = ''
    desc = '1-Wire bus and MicroLan'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['onewire']
    probes = [
        {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
    ]
    optional_probes = [
        {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
    ]
    options = {
        'overdrive': ['Overdrive', 0],
    }
    annotations = [
        ['ASCII', 'Data bytes as ASCII characters'],
        ['Decimal', 'Databytes as decimal, integer values'],
        ['Hex', 'Data bytes in hex format'],
        ['Octal', 'Data bytes as octal numbers'],
        ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
    ]

    def putx(self, data):
        self.put(self.startsample, self.samplenum - 1, self.out_ann, data)

    def __init__(self, **kwargs):
        # Common variables
        self.samplenum = 0
        # Link layer variables
        self.lnk_state = 'WAIT FOR NEGEDGE'
        self.lnk_event = 'NONE'
        self.lnk_start = -1
        self.lnk_bit   = -1
        self.lnk_cnt   = 0
        self.lnk_byte  = -1
        # Network layer variables
        self.net_state = 'WAIT FOR EVENT'
        self.net_event = 'NONE'
        self.net_command = -1
        # Transport layer variables
        self.trn_state = 'WAIT FOR EVENT'
        self.trn_event = 'NONE'

        self.data_sample = -1
        self.cur_data_bit = 0
        self.databyte = 0
        self.startsample = -1

    def start(self, metadata):
        self.samplerate = metadata['samplerate']
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')

        # The width of the 1-Wire time base (30us) in number of samples.
        # TODO: optimize this value
        self.time_base = float(self.samplerate) / float(0.000030)

    def report(self):
        pass

    def get_data_sample(self, owr):
        # Skip samples until we're in the middle of the start bit.
        if not self.reached_data_sample():
            return

        self.data_sample = owr

        self.cur_data_bit = 0
        self.databyte = 0
        self.startsample = -1

        self.state = 'GET DATA BITS'

        self.put(self.cycle_start, self.samplenum, self.out_proto,
                 ['STARTBIT', self.startbit])
        self.put(self.cycle_start, self.samplenum, self.out_ann,
                 [ANN_ASCII, ['Start bit', 'Start', 'S']])

    def get_data_bits(self, owr):
        # Skip samples until we're in the middle of the desired data bit.
        if not self.reached_bit(self.cur_data_bit + 1):
            return

        # Save the sample number where the data byte starts.
        if self.startsample == -1:
            self.startsample = self.samplenum

        # Get the next data bit in LSB-first or MSB-first fashion.
        if self.options['bit_order'] == 'lsb-first':
            self.databyte >>= 1
            self.databyte |= \
                (owr << (self.options['num_data_bits'] - 1))
        elif self.options['bit_order'] == 'msb-first':
            self.databyte <<= 1
            self.databyte |= (owr << 0)
        else:
            raise Exception('Invalid bit order value: %s',
                            self.options['bit_order'])

        # Return here, unless we already received all data bits.
        # TODO? Off-by-one?
        if self.cur_data_bit < self.options['num_data_bits'] - 1:
            self.cur_data_bit += 1
            return

        self.state = 'GET PARITY BIT'

        self.put(self.startsample, self.samplenum - 1, self.out_proto,
                 ['DATA', self.databyte])

        self.putx([ANN_ASCII, [chr(self.databyte)]])
        self.putx([ANN_DEC,   [str(self.databyte)]])
        self.putx([ANN_HEX,   [hex(self.databyte),
                               hex(self.databyte)[2:]]])
        self.putx([ANN_OCT,   [oct(self.databyte),
                               oct(self.databyte)[2:]]])
        self.putx([ANN_BITS,  [bin(self.databyte),
                               bin(self.databyte)[2:]]])

    def decode(self, ss, es, data):
        for (self.samplenum, owr) in data:

            # Data link layer

            # Clear events.
            self.lnk_event = "RESET"
            # State machine.
            if self.lnk_state == 'WAIT FOR FALLING EDGE':
                # The start of a cycle is a falling edge.
                if (owr == 0):
                    # Save the sample number for the falling edge.
                    self.lnk_fall = self.samplenum
                    # Go to waiting for sample time
                    self.lnk_state = 'WAIT FOR DATA SAMPLE'
            elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum - self.lnk_fall == 1*self.time_base):
                    self.lnk_bit  = owr & 0x1
                    self.lnk_event = "DATA BIT"
                    if (self.lnk_bit) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                    else              :  self.lnk_state = 'WAIT FOR RISING EDGE'
            elif self.lnk_state == 'WAIT FOR RISING EDGE':
                # The end of a cycle is a rising edge.
                if (owr == 1):
                    # A reset cycle is longer than 8T
                    if (self.samplenum - self.lnk_fall > 8*self.time_base):
                        # Save the sample number for the falling edge.
                        self.lnk_rise = self.samplenum
                        # Send a reset event to the next protocol layer
                        self.lnk_event = "RESET"
                        self.lnk_state = "WAIT FOR PRESENCE DETECT"
            elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
                    self.lnk_bit  = owr & 0x1
                    self.lnk_event = "PRESENCE DETECT"
                    if (self.lnk_bit) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                    else              :  self.lnk_state = 'WAIT FOR RISING EDGE'
            else:
                raise Exception('Invalid lnk_state: %d' % self.lnk_state)

            # Network layer
            
            # Clear events.
            self.net_event = "RESET"
            # State machine.
            if self.lnk_event == "RESET":
                self.net_state = "WAIT FOR COMMAND"
                self.net_cnt = 0
                self.net_cmd = 0
            elif self.lnk_event == "DATA BIT"
                if self.net_state == "WAIT FOR COMMAND"
                    self.net_cnt = self.net_cnt + 1
                    self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
                    if (self.lnk_cnt == 8)
                        self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
                        if self.net_cmd == 0x33:
                            # READ ROM
                        elif self.net_cmd == 0x0f
                            # READ ROM
                        elif self.net_cmd == 0xcc
                            # SKIP ROM
                        elif self.net_cmd == 0x55
                            # MATCH ROM
                        elif self.net_cmd == 0xf0
                            # SEARCH ROM
                        elif self.net_cmd == 0x3c
                            # OVERDRIVE SKIP ROM
                        elif self.net_cmd == 0x69
                            # OVERDRIVE MATCH ROM
                        self.lnk_cnt = 0
                if self.net_state == "WAIT FOR ROM":
                    #
                else:
                    raise Exception('Invalid net_state: %d' % self.net_state)
            elif not (self.lnk_event == "NONE"):
                raise Exception('Invalid net_event: %d' % self.net_event)


                    if (self.samplenum == self.lnk_start + 8*self.time_base):
                        self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
Commit	Line	Data
51990c45 IJ	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# 1-Wire protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# Annotation feed formats
	26	ANN_ASCII = 0
	27	ANN_DEC = 1
	28	ANN_HEX = 2
	29	ANN_OCT = 3
	30	ANN_BITS = 4
	31
	32	class Decoder(srd.Decoder):
	33	api_version = 1
	34	id = 'onewire'
	35	name = '1-Wire'
	36	longname = ''
	37	desc = '1-Wire bus and MicroLan'
	38	license = 'gplv2+'
	39	inputs = ['logic']
	40	outputs = ['onewire']
	41	probes = [
	42	{'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
	43	]
	44	optional_probes = [
	45	{'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
	46	]
	47	options = {
	48	'overdrive': ['Overdrive', 0],
	49	}
	50	annotations = [
	51	['ASCII', 'Data bytes as ASCII characters'],
	52	['Decimal', 'Databytes as decimal, integer values'],
	53	['Hex', 'Data bytes in hex format'],
	54	['Octal', 'Data bytes as octal numbers'],
	55	['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
	56	]
	57
	58	def putx(self, data):
	59	self.put(self.startsample, self.samplenum - 1, self.out_ann, data)
	60
	61	def __init__(self, **kwargs):
	62	# Common variables
	63	self.samplenum = 0
	64	# Link layer variables
39a0219a	65	self.lnk_state = 'WAIT FOR NEGEDGE'
51990c45 IJ	66	self.lnk_event = 'NONE'
	67	self.lnk_start = -1
	68	self.lnk_bit = -1
	69	self.lnk_cnt = 0
	70	self.lnk_byte = -1
	71	# Network layer variables
	72	self.net_state = 'WAIT FOR EVENT'
	73	self.net_event = 'NONE'
	74	self.net_command = -1
	75	# Transport layer variables
	76	self.trn_state = 'WAIT FOR EVENT'
	77	self.trn_event = 'NONE'
	78
	79	self.data_sample = -1
	80	self.cur_data_bit = 0
	81	self.databyte = 0
	82	self.startsample = -1
	83
	84	def start(self, metadata):
	85	self.samplerate = metadata['samplerate']
	86	self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
	87	self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')
	88
	89	# The width of the 1-Wire time base (30us) in number of samples.
	90	# TODO: optimize this value
	91	self.time_base = float(self.samplerate) / float(0.000030)
	92
	93	def report(self):
	94	pass
	95
	96	def get_data_sample(self, owr):
	97	# Skip samples until we're in the middle of the start bit.
	98	if not self.reached_data_sample():
	99	return
	100
	101	self.data_sample = owr
	102
	103	self.cur_data_bit = 0
	104	self.databyte = 0
	105	self.startsample = -1
	106
	107	self.state = 'GET DATA BITS'
	108
	109	self.put(self.cycle_start, self.samplenum, self.out_proto,
	110	['STARTBIT', self.startbit])
	111	self.put(self.cycle_start, self.samplenum, self.out_ann,
	112	[ANN_ASCII, ['Start bit', 'Start', 'S']])
	113
	114	def get_data_bits(self, owr):
	115	# Skip samples until we're in the middle of the desired data bit.
	116	if not self.reached_bit(self.cur_data_bit + 1):
	117	return
	118
	119	# Save the sample number where the data byte starts.
	120	if self.startsample == -1:
	121	self.startsample = self.samplenum
	122
	123	# Get the next data bit in LSB-first or MSB-first fashion.
	124	if self.options['bit_order'] == 'lsb-first':
	125	self.databyte >>= 1
	126	self.databyte \|= \
	127	(owr << (self.options['num_data_bits'] - 1))
	128	elif self.options['bit_order'] == 'msb-first':
	129	self.databyte <<= 1
130	self.databyte \|= (owr << 0)
131	else:
132	raise Exception('Invalid bit order value: %s',
133	self.options['bit_order'])
134
135	# Return here, unless we already received all data bits.
136	# TODO? Off-by-one?
137	if self.cur_data_bit < self.options['num_data_bits'] - 1:
138	self.cur_data_bit += 1
139	return
140
141	self.state = 'GET PARITY BIT'
142
143	self.put(self.startsample, self.samplenum - 1, self.out_proto,
144	['DATA', self.databyte])
145
146	self.putx([ANN_ASCII, [chr(self.databyte)]])
147	self.putx([ANN_DEC, [str(self.databyte)]])
148	self.putx([ANN_HEX, [hex(self.databyte),
149	hex(self.databyte)[2:]]])
150	self.putx([ANN_OCT, [oct(self.databyte),
151	oct(self.databyte)[2:]]])
152	self.putx([ANN_BITS, [bin(self.databyte),
153	bin(self.databyte)[2:]]])
154
155	def decode(self, ss, es, data):
156	for (self.samplenum, owr) in data:
157
51990c45	158	# Data link layer
39a0219a IJ	159
	160	# Clear events.
	161	self.lnk_event = "RESET"
	162	# State machine.
51990c45 IJ	163	if self.lnk_state == 'WAIT FOR FALLING EDGE':
51990c45 IJ	164	# The start of a cycle is a falling edge.
39a0219a IJ	165	if (owr == 0):
	166	# Save the sample number for the falling edge.
	167	self.lnk_fall = self.samplenum
51990c45	168	# Go to waiting for sample time
39a0219a IJ	169	self.lnk_state = 'WAIT FOR DATA SAMPLE'
39a0219a IJ	170	elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
51990c45	171	# Data should be sample one 'time unit' after a falling edge
39a0219a	172	if (self.samplenum - self.lnk_fall == 1*self.time_base):
51990c45	173	self.lnk_bit = owr & 0x1
39a0219a IJ	174	self.lnk_event = "DATA BIT"
	175	if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
	176	else : self.lnk_state = 'WAIT FOR RISING EDGE'
51990c45 IJ	177	elif self.lnk_state == 'WAIT FOR RISING EDGE':
51990c45 IJ	178	# The end of a cycle is a rising edge.
39a0219a IJ	179	if (owr == 1):
	180	# A reset cycle is longer than 8T
	181	if (self.samplenum - self.lnk_fall > 8*self.time_base):
	182	# Save the sample number for the falling edge.
	183	self.lnk_rise = self.samplenum
	184	# Send a reset event to the next protocol layer
	185	self.lnk_event = "RESET"
	186	self.lnk_state = "WAIT FOR PRESENCE DETECT"
	187	elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
	188	# Data should be sample one 'time unit' after a falling edge
	189	if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
	190	self.lnk_bit = owr & 0x1
	191	self.lnk_event = "PRESENCE DETECT"
	192	if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
	193	else : self.lnk_state = 'WAIT FOR RISING EDGE'
	194	else:
	195	raise Exception('Invalid lnk_state: %d' % self.lnk_state)
	196
	197	# Network layer
	198
	199	# Clear events.
	200	self.net_event = "RESET"
	201	# State machine.
	202	if self.lnk_event == "RESET":
	203	self.net_state = "WAIT FOR COMMAND"
	204	self.net_cnt = 0
	205	self.net_cmd = 0
	206	elif self.lnk_event == "DATA BIT"
	207	if self.net_state == "WAIT FOR COMMAND"
	208	self.net_cnt = self.net_cnt + 1
	209	self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
	210	if (self.lnk_cnt == 8)
	211	self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
	212	if self.net_cmd == 0x33:
	213	# READ ROM
	214	elif self.net_cmd == 0x0f
	215	# READ ROM
	216	elif self.net_cmd == 0xcc
	217	# SKIP ROM
	218	elif self.net_cmd == 0x55
	219	# MATCH ROM
	220	elif self.net_cmd == 0xf0
	221	# SEARCH ROM
	222	elif self.net_cmd == 0x3c
	223	# OVERDRIVE SKIP ROM
	224	elif self.net_cmd == 0x69
	225	# OVERDRIVE MATCH ROM
	226	self.lnk_cnt = 0
	227	if self.net_state == "WAIT FOR ROM":
	228	#
	229	else:
	230	raise Exception('Invalid net_state: %d' % self.net_state)
	231	elif not (self.lnk_event == "NONE"):
	232	raise Exception('Invalid net_event: %d' % self.net_event)
51990c45	233
51990c45	234
51990c45	235
39a0219a IJ	236	if (self.samplenum == self.lnk_start + 8*self.time_base):
39a0219a IJ	237	self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])