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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
4539e9ca 17## along with this program; if not, see <http://www.gnu.org/licenses/>.
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18##
19
20import sigrokdecode as srd
07505b2a 21from .lists import *
fecabafe 22
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23TX, RX = range(2)
24
fecabafe 25class Decoder(srd.Decoder):
b197383c 26 api_version = 3
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27 id = 'mrf24j40'
28 name = 'MRF24J40'
29 longname = 'Microchip MRF24J40'
30 desc = 'IEEE 802.15.4 2.4 GHz RF tranceiver chip.'
9eac0fe3 31 license = 'gplv2+'
fecabafe 32 inputs = ['spi']
6cbba91f 33 outputs = []
d6d8a8a4 34 tags = ['IC', 'Wireless/RF']
fecabafe 35 annotations = (
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36 ('sread', 'Short register read'),
37 ('swrite', 'Short register write'),
38 ('lread', 'Long register read'),
39 ('lwrite', 'Long register write'),
40 ('warning', 'Warning'),
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41 ('tx-frame', 'TX frame'),
42 ('rx-frame', 'RX frame'),
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43 ('tx-retry-1', '1x TX retry'),
44 ('tx-retry-2', '2x TX retry'),
45 ('tx-retry-3', '3x TX retry'),
46 ('tx-fail', 'TX fail (too many retries)'),
47 ('ccafail', 'CCAFAIL (channel busy)'),
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48 )
49 annotation_rows = (
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50 ('reads', 'Reads', (0, 2)),
51 ('writes', 'Writes', (1, 3)),
fecabafe 52 ('warnings', 'Warnings', (4,)),
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53 ('tx-frames', 'TX frames', (5,)),
54 ('rx-frames', 'RX frames', (6,)),
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55 ('tx-retries-1', '1x TX retries', (7,)),
56 ('tx-retries-2', '2x TX retries', (8,)),
57 ('tx-retries-3', '3x TX retries', (9,)),
58 ('tx-fails', 'TX fails', (10,)),
59 ('ccafails', 'CCAFAILs', (11,)),
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60 )
61
92b7b49f 62 def __init__(self):
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63 self.reset()
64
65 def reset(self):
fecabafe 66 self.ss_cmd, self.es_cmd = 0, 0
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67 self.ss_frame, self.es_frame = [0, 0], [0, 0]
68 self.mosi_bytes, self.miso_bytes = [], []
69 self.framecache = [[], []]
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70
71 def start(self):
72 self.out_ann = self.register(srd.OUTPUT_ANN)
73
74 def putx(self, data):
75 self.put(self.ss_cmd, self.es_cmd, self.out_ann, data)
76
77 def putw(self, pos, msg):
78 self.put(pos[0], pos[1], self.out_ann, [4, [msg]])
79
89256c6c 80 def reset_data(self):
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81 self.mosi_bytes = []
82 self.miso_bytes = []
83
84 def handle_short(self):
85 write = self.mosi_bytes[0] & 0x1
86 reg = (self.mosi_bytes[0] >> 1) & 0x3f
87 reg_desc = sregs.get(reg, 'illegal')
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88 for rxtx in (RX, TX):
89 if self.framecache[rxtx] == []:
90 continue
91 bit0 = self.mosi_bytes[1] & (1 << 0)
92 if rxtx == TX and not (reg_desc == 'TXNCON' and bit0 == 1):
93 continue
94 if rxtx == RX and not (reg_desc == 'RXFLUSH' and bit0 == 1):
95 continue
96 idx = 5 if rxtx == TX else 6
97 xmitdir = 'TX' if rxtx == TX else 'RX'
98 frame = ' '.join(['%02X' % b for b in self.framecache[rxtx]])
99 self.put(self.ss_frame[rxtx], self.es_frame[rxtx], self.out_ann,
100 [idx, ['%s frame: %s' % (xmitdir, frame)]])
101 self.framecache[rxtx] = []
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102 if write:
103 self.putx([1, ['%s: %#x' % (reg_desc, self.mosi_bytes[1])]])
104 else:
105 self.putx([0, ['%s: %#x' % (reg_desc, self.miso_bytes[1])]])
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106 numretries = (self.miso_bytes[1] & 0xc0) >> 6
107 if reg_desc == 'TXSTAT' and numretries > 0:
108 txfail = 1 if ((self.miso_bytes[1] & (1 << 0)) != 0) else 0
109 idx = 6 + numretries + txfail
110 if txfail:
111 self.putx([idx, ['TX fail (>= 4 retries)', 'TX fail']])
112 else:
113 self.putx([idx, ['TX retries: %d' % numretries]])
114 if reg_desc == 'TXSTAT' and (self.miso_bytes[1] & (1 << 5)) != 0:
115 self.putx([11, ['CCAFAIL (channel busy)', 'CCAFAIL']])
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116
117 def handle_long(self):
118 dword = self.mosi_bytes[0] << 8 | self.mosi_bytes[1]
119 write = dword & (0x1 << 4)
120 reg = dword >> 5 & 0x3ff
121 if reg >= 0x0:
122 reg_desc = 'TX:%#x' % reg
123 if reg >= 0x80:
124 reg_desc = 'TX beacon:%#x' % reg
125 if reg >= 0x100:
126 reg_desc = 'TX GTS1:%#x' % reg
127 if reg >= 0x180:
128 reg_desc = 'TX GTS2:%#x' % reg
129 if reg >= 0x200:
130 reg_desc = lregs.get(reg, 'illegal')
131 if reg >= 0x280:
132 reg_desc = 'Security keys:%#x' % reg
133 if reg >= 0x2c0:
134 reg_desc = 'Reserved:%#x' % reg
135 if reg >= 0x300:
136 reg_desc = 'RX:%#x' % reg
137
138 if write:
139 self.putx([3, ['%s: %#x' % (reg_desc, self.mosi_bytes[2])]])
140 else:
141 self.putx([2, ['%s: %#x' % (reg_desc, self.miso_bytes[2])]])
142
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143 for rxtx in (RX, TX):
144 if rxtx == RX and reg_desc[:3] != 'RX:':
145 continue
146 if rxtx == TX and reg_desc[:3] != 'TX:':
147 continue
148 if len(self.framecache[rxtx]) == 0:
149 self.ss_frame[rxtx] = self.ss_cmd
150 self.es_frame[rxtx] = self.es_cmd
151 self.framecache[rxtx] += [self.mosi_bytes[2]] if rxtx == TX else [self.miso_bytes[2]]
152
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153 def decode(self, ss, es, data):
154 ptype = data[0]
155 if ptype == 'CS-CHANGE':
156 # If we transition high mid-stream, toss out our data and restart.
157 cs_old, cs_new = data[1:]
158 if cs_old is not None and cs_old == 0 and cs_new == 1:
159 if len(self.mosi_bytes) not in (0, 2, 3):
160 self.putw([self.ss_cmd, es], 'Misplaced CS!')
89256c6c 161 self.reset_data()
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162 return
163
164 # Don't care about anything else.
165 if ptype != 'DATA':
166 return
167 mosi, miso = data[1:]
168
169 self.ss, self.es = ss, es
170
171 if len(self.mosi_bytes) == 0:
172 self.ss_cmd = ss
173 self.mosi_bytes.append(mosi)
174 self.miso_bytes.append(miso)
175
176 # Everything is either 2 bytes or 3 bytes.
177 if len(self.mosi_bytes) < 2:
178 return
179
180 if self.mosi_bytes[0] & 0x80:
181 if len(self.mosi_bytes) == 3:
182 self.es_cmd = es
183 self.handle_long()
89256c6c 184 self.reset_data()
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185 else:
186 self.es_cmd = es
187 self.handle_short()
89256c6c 188 self.reset_data()