[libsigrokdecode.git] / decoders / lpc / lpc.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# LPC protocol decoder

import sigrokdecode as srd

# Annotation feed formats
ANN_ASCII = 0

# ...
fields = {
    # START field (indicates start or stop of a transaction)
    'START': {
        0b0000: 'Start of cycle for a target',
        0b0001: 'Reserved',
        0b0010: 'Grant for bus master 0',
        0b0011: 'Grant for bus master 1',
        0b0100: 'Reserved',
        0b0101: 'Reserved',
        0b0110: 'Reserved',
        0b0111: 'Reserved',
        0b1000: 'Reserved',
        0b1001: 'Reserved',
        0b1010: 'Reserved',
        0b1011: 'Reserved',
        0b1100: 'Reserved',
        0b1101: 'Start of cycle for a Firmware Memory Read cycle',
        0b1110: 'Start of cycle for a Firmware Memory Write cycle',
        0b1111: 'Stop/abort (end of a cycle for a target)',
    },
    # Cycle type / direction field
    # Bit 0 (LAD[0]) is unused, should always be 0.
    # Neither host nor peripheral are allowed to drive 0b11x0.
    'CT_DR': {
        0b0000: 'I/O read',
        0b0010: 'I/O write',
        0b0100: 'Memory read',
        0b0110: 'Memory write',
        0b1000: 'DMA read',
        0b1010: 'DMA write',
        0b1100: 'Reserved / not allowed',
        0b1110: 'Reserved / not allowed',
    },
    # SIZE field (determines how many bytes are to be transferred)
    # Bits[3:2] are reserved, must be driven to 0b00.
    # Neither host nor peripheral are allowed to drive 0b0010.
    'SIZE': {
        0b0000: '8 bits (1 byte)',
        0b0001: '16 bits (2 bytes)',
        0b0010: 'Reserved / not allowed',
        0b0011: '32 bits (4 bytes)',
    },
    # CHANNEL field (bits[2:0] contain the DMA channel number)
    'CHANNEL': {
        0b0000: '0',
        0b0001: '1',
        0b0010: '2',
        0b0011: '3',
        0b0100: '4',
        0b0101: '5',
        0b0110: '6',
        0b0111: '7',
    },
    # SYNC field (used to add wait states)
    'SYNC': {
        0b0000: 'Ready',
        0b0001: 'Reserved',
        0b0010: 'Reserved',
        0b0011: 'Reserved',
        0b0100: 'Reserved',
        0b0101: 'Short wait',
        0b0110: 'Long wait',
        0b0111: 'Reserved',
        0b1000: 'Reserved',
        0b1001: 'Ready more (DMA only)',
        0b1010: 'Error',
        0b1011: 'Reserved',
        0b1100: 'Reserved',
        0b1101: 'Reserved',
        0b1110: 'Reserved',
        0b1111: 'Reserved',
    },
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'lpc'
    name = 'LPC'
    longname = 'Low-Pin-Count'
    desc = 'TODO.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['lpc']
    probes = [
        {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'},
        {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
        {'id': 'lclk',   'name': 'LCLK',    'desc': 'TODO'},
        {'id': 'lad0',   'name': 'LAD[0]',  'desc': 'TODO'},
        {'id': 'lad1',   'name': 'LAD[1]',  'desc': 'TODO'},
        {'id': 'lad2',   'name': 'LAD[2]',  'desc': 'TODO'},
        {'id': 'lad3',   'name': 'LAD[3]',  'desc': 'TODO'},
    ]
    optional_probes = [
        {'id': 'ldrq',   'name': 'LDRQ#',   'desc': 'TODO'},
        {'id': 'serirq', 'name': 'SERIRQ',  'desc': 'TODO'},
        {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'},
        {'id': 'lpme',   'name': 'LPME#',   'desc': 'TODO'},
        {'id': 'lpcpd',  'name': 'LPCPD#',  'desc': 'TODO'},
        {'id': 'lsmi',   'name': 'LSMI#',   'desc': 'TODO'},
    ]
    options = {}
    annotations = [
        ['ASCII', 'TODO: description'],
    ]

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.oldlclk = -1
        self.samplenum = 0
        self.clocknum = 0
        self.lad = -1
        self.addr = 0
        self.cur_nibble = 0
        self.cycle_type = -1
        self.oldpins = (-1, -1, -1, -1, -1, -1, -1)

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc')

    def report(self):
        pass

    def handle_get_start(self, lad, lframe):
        # LAD[3:0]: START field (1 clock cycle).

        # The last value of LAD[3:0] before LFRAME# gets de-asserted is what
        # the peripherals must use. However, the host can keep LFRAME# asserted
        # multiple clocks, and we output all START fields that occur, even
        # though the peripherals are supposed to ignore all but the last one.
        s = fields['START'][lad]
        self.put(0, 0, self.out_ann, [0, [s]])

        # Output a warning if LAD[3:0] changes while LFRAME# is low.
        # TODO
        if (self.lad != -1 and self.lad != lad):
            self.put(0, 0, self.out_ann,
                     [0, ['Warning: LAD[3:0] changed while '
                     'LFRAME# was asserted']])

        # LFRAME# is asserted (low). Wait until it gets de-asserted again
        # (the host is allowed to keep it asserted multiple clocks).
        if lframe != 1:
            return

        self.start_field = self.lad
        self.state = 'GET CT/DR'

    def handle_get_ct_dr(self, lad, lad_bits):
        # LAD[3:0]: Cycle type / direction field (1 clock cycle).

        self.cycle_type = fields['CT_DR'][lad]

        # TODO: Warning/error on invalid cycle types.
        if self.cycle_type == 'Reserved':
            self.put(0, 0, self.out_ann,
                     [0, ['Warning: Invalid cycle type (%s)' % lad_bits]])

        # ...
        self.put(0, 0, self.out_ann, [0, ['Cycle type: %s' % self.cycle_type]])

        self.state = 'GET ADDR'
        self.addr = 0
        self.cur_nibble = 0

    def handle_get_addr(self, lad, lad_bits):
        # LAD[3:0]: ADDR field (4/8/0 clock cycles).

        # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks.
        # DMA cycles: no ADDR clocks at all.
        if self.cycle_type in ('I/O read', 'I/O write'):
            addr_nibbles = 4 # Address is 16bits.
        elif self.cycle_type in ('Memory read', 'Memory write'):
            addr_nibbles = 8 # Address is 32bits.
        else:
            addr_nibbles = 0 # TODO: How to handle later on?

        # Data is driven MSN-first.
        offset = ((addr_nibbles - 1) - self.cur_nibble) * 4
        self.addr |= (lad << offset)

        # Continue if we haven't seen all ADDR cycles, yet.
        # TODO: Off-by-one?
        if (self.cur_nibble < addr_nibbles - 1):
            self.cur_nibble += 1
            return

        self.put(0, 0, self.out_ann, [0, ['Address: %s' % hex(self.addr)]])

        self.state = 'GET TAR'
        self.tar_count = 0

    def handle_get_tar(self, lad, lad_bits):
        # LAD[3:0]: First TAR (turn-around) field (2 clock cycles).

        self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s'
                 % (self.tarcount, lad_bits)]])

        # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
        # either the host or peripheral. On the second clock cycle,
        # the host or peripheral tri-states LAD[3:0], but its value
        # should still be 1111, due to pull-ups on the LAD lines.
        if lad_bits != '1111':
            self.put(0, 0, self.out_ann,
                     [0, ['Warning: TAR, cycle %d: %s (expected 1111)'
                     % (self.tarcount, lad_bits)]])

        if (self.tarcount != 2):
            self.tarcount += 1
            return

        self.state = 'GET SYNC'

    def handle_get_sync(self, lad, lad_bits):
        # LAD[3:0]: SYNC field (1-n clock cycles).

        self.sync_val = lad_bits
        self.cycle_type = fields['SYNC'][lad]

        # TODO: Warnings if reserved value are seen?
        if self.cycle_type == 'Reserved':
            self.put(0, 0, self.out_ann, [0, ['Warning: SYNC, cycle %d: %s '
                     '(reserved value)' % (self.synccount, self.sync_val)]])

        self.put(0, 0, self.out_ann, [0, ['SYNC, cycle %d: %s'
                 % (self.synccount, self.sync_val)]])

        # TODO

        self.state = 'GET DATA'
        self.cycle_count = 0

    def handle_get_data(self, lad, lad_bits):
        # LAD[3:0]: DATA field (2 clock cycles).

        if (self.cycle_count == 0):
            self.databyte = lad
        elif (self.cycle_count == 1):
            self.databyte |= (lad << 4)
        else:
            pass # TODO: Error?

        if (self.cycle_count != 2):
            self.cycle_count += 1
            return

        self.put(0, 0, self.out_ann, [0, ['DATA: %s' % hex(self.databyte)]])
        
        self.state = 'GET TAR2'

    def handle_get_tar2(self, lad, lad_bits):
        # LAD[3:0]: Second TAR field (2 clock cycles).

        self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s'
                 % (self.tarcount, lad_bits)]])

        # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
        # either the host or peripheral. On the second clock cycle,
        # the host or peripheral tri-states LAD[3:0], but its value
        # should still be 1111, due to pull-ups on the LAD lines.
        if lad_bits != '1111':
            self.put(0, 0, self.out_ann,
                     [0, ['Warning: TAR, cycle %d: %s (expected 1111)'
                     % (self.tarcount, lad_bits)]])

        if (self.tarcount != 2):
            self.tarcount += 1
            return

        self.state = 'GET SYNC'

    # TODO: At which edge of the clock is data latched? Falling?
    def decode(self, ss, es, data):
        for (samplenum, pins) in data:

            # If none of the pins changed, there's nothing to do.
            if self.oldpins == pins:
                continue

            # Store current pin values for the next round.
            self.oldpins = pins

            # Get individual pin values into local variables.
            # TODO: Handle optional pins.
            (lframe, lreset, lclk, lad0, lad1, lad2, lad3) = pins

            # Only look at the signals upon falling LCLK edges.
            # TODO: Rising?
            ## if not (self.oldlclk == 1 and lclk == 0)
            ##     self.oldlclk = lclk
            ##     continue

            # Store LAD[3:0] bit values (one nibble) in local variables.
            # Most (but not all) states need this.
            if self.state != 'IDLE':
                lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
                lad_bits = bin(lad)[2:]

            # State machine
            if self.state == 'IDLE':
                # A valid LPC cycle starts with LFRAME# being asserted (low).
                # TODO?
                if lframe != 0:
                   continue
                self.state = 'GET START'
                self.lad = -1
                # self.clocknum = 0
            elif self.state == 'GET START':
                handle_get_start(lad, lad_bits, lframe)
            elif self.state == 'GET CT/DR':
                handle_get_ct_dr(lad, lad_bits)
            elif self.state == 'GET ADDR':
                handle_get_addr(lad, lad_bits)
            elif self.state == 'GET TAR':
                handle_get_tar(lad, lad_bits)
            elif self.state == 'GET SYNC':
                handle_get_sync(lad, lad_bits)
            elif self.state == 'GET DATA':
                handle_get_data(lad, lad_bits)
            elif self.state == 'GET TAR2':
                handle_get_tar2(lad, lad_bits)
            else:
                raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
271acd3b UH	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# LPC protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# Annotation feed formats
	26	ANN_ASCII = 0
	27
	28	# ...
	29	fields = {
2002229d UH	30	# START field (indicates start or stop of a transaction)
2002229d UH	31	'START': {
271acd3b UH	32	0b0000: 'Start of cycle for a target',
	33	0b0001: 'Reserved',
	34	0b0010: 'Grant for bus master 0',
	35	0b0011: 'Grant for bus master 1',
	36	0b0100: 'Reserved',
	37	0b0101: 'Reserved',
	38	0b0110: 'Reserved',
	39	0b0111: 'Reserved',
	40	0b1000: 'Reserved',
	41	0b1001: 'Reserved',
	42	0b1010: 'Reserved',
	43	0b1011: 'Reserved',
	44	0b1100: 'Reserved',
	45	0b1101: 'Start of cycle for a Firmware Memory Read cycle',
	46	0b1110: 'Start of cycle for a Firmware Memory Write cycle',
2002229d	47	0b1111: 'Stop/abort (end of a cycle for a target)',
271acd3b	48	},
2002229d UH	49	# Cycle type / direction field
	50	# Bit 0 (LAD[0]) is unused, should always be 0.
	51	# Neither host nor peripheral are allowed to drive 0b11x0.
	52	'CT_DR': {
271acd3b UH	53	0b0000: 'I/O read',
	54	0b0010: 'I/O write',
	55	0b0100: 'Memory read',
	56	0b0110: 'Memory write',
	57	0b1000: 'DMA read',
	58	0b1010: 'DMA write',
2002229d UH	59	0b1100: 'Reserved / not allowed',
	60	0b1110: 'Reserved / not allowed',
	61	},
	62	# SIZE field (determines how many bytes are to be transferred)
	63	# Bits[3:2] are reserved, must be driven to 0b00.
	64	# Neither host nor peripheral are allowed to drive 0b0010.
	65	'SIZE': {
	66	0b0000: '8 bits (1 byte)',
	67	0b0001: '16 bits (2 bytes)',
	68	0b0010: 'Reserved / not allowed',
	69	0b0011: '32 bits (4 bytes)',
	70	},
	71	# CHANNEL field (bits[2:0] contain the DMA channel number)
	72	'CHANNEL': {
	73	0b0000: '0',
	74	0b0001: '1',
	75	0b0010: '2',
	76	0b0011: '3',
	77	0b0100: '4',
	78	0b0101: '5',
	79	0b0110: '6',
	80	0b0111: '7',
271acd3b	81	},
2002229d	82	# SYNC field (used to add wait states)
271acd3b UH	83	'SYNC': {
	84	0b0000: 'Ready',
	85	0b0001: 'Reserved',
	86	0b0010: 'Reserved',
	87	0b0011: 'Reserved',
	88	0b0100: 'Reserved',
	89	0b0101: 'Short wait',
	90	0b0110: 'Long wait',
	91	0b0111: 'Reserved',
	92	0b1000: 'Reserved',
	93	0b1001: 'Ready more (DMA only)',
	94	0b1010: 'Error',
	95	0b1011: 'Reserved',
	96	0b1100: 'Reserved',
	97	0b1101: 'Reserved',
	98	0b1110: 'Reserved',
	99	0b1111: 'Reserved',
	100	},
	101	}
	102
	103	class Decoder(srd.Decoder):
	104	api_version = 1
	105	id = 'lpc'
	106	name = 'LPC'
	107	longname = 'Low-Pin-Count'
	108	desc = 'TODO.'
	109	license = 'gplv2+'
	110	inputs = ['logic']
	111	outputs = ['lpc']
	112	probes = [
	113	{'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'},
	114	{'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
	115	{'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'},
	116	{'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'},
	117	{'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'},
	118	{'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'},
	119	{'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'},
	120	]
	121	optional_probes = [
	122	{'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'},
	123	{'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'},
	124	{'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'},
	125	{'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'},
	126	{'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'},
	127	{'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'},
	128	]
	129	options = {}
	130	annotations = [
	131	['ASCII', 'TODO: description'],
	132	]
	133
	134	def __init__(self, **kwargs):
	135	self.state = 'IDLE'
	136	self.oldlclk = -1
	137	self.samplenum = 0
	138	self.clocknum = 0
	139	self.lad = -1
	140	self.addr = 0
	141	self.cur_nibble = 0
	142	self.cycle_type = -1
	143	self.oldpins = (-1, -1, -1, -1, -1, -1, -1)
	144
	145	def start(self, metadata):
	146	self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc')
147	self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc')
148
149	def report(self):
150	pass
151
152	def handle_get_start(self, lad, lframe):
153	# LAD[3:0]: START field (1 clock cycle).
154
155	# The last value of LAD[3:0] before LFRAME# gets de-asserted is what
156	# the peripherals must use. However, the host can keep LFRAME# asserted
157	# multiple clocks, and we output all START fields that occur, even
158	# though the peripherals are supposed to ignore all but the last one.
159	s = fields['START'][lad]
160	self.put(0, 0, self.out_ann, [0, [s]])
161
162	# Output a warning if LAD[3:0] changes while LFRAME# is low.
163	# TODO
164	if (self.lad != -1 and self.lad != lad):
165	self.put(0, 0, self.out_ann,
166	[0, ['Warning: LAD[3:0] changed while '
167	'LFRAME# was asserted']])
168
169	# LFRAME# is asserted (low). Wait until it gets de-asserted again
170	# (the host is allowed to keep it asserted multiple clocks).
171	if lframe != 1:
172	return
173
174	self.start_field = self.lad
175	self.state = 'GET CT/DR'
176
177	def handle_get_ct_dr(self, lad, lad_bits):
178	# LAD[3:0]: Cycle type / direction field (1 clock cycle).
179
180	self.cycle_type = fields['CT_DR'][lad]
181
182	# TODO: Warning/error on invalid cycle types.
183	if self.cycle_type == 'Reserved':
184	self.put(0, 0, self.out_ann,
185	[0, ['Warning: Invalid cycle type (%s)' % lad_bits]])
186
187	# ...
188	self.put(0, 0, self.out_ann, [0, ['Cycle type: %s' % self.cycle_type]])
189
190	self.state = 'GET ADDR'
191	self.addr = 0
192	self.cur_nibble = 0
193
194	def handle_get_addr(self, lad, lad_bits):
195	# LAD[3:0]: ADDR field (4/8/0 clock cycles).
196
197	# I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks.
198	# DMA cycles: no ADDR clocks at all.
199	if self.cycle_type in ('I/O read', 'I/O write'):
200	addr_nibbles = 4 # Address is 16bits.
201	elif self.cycle_type in ('Memory read', 'Memory write'):
202	addr_nibbles = 8 # Address is 32bits.
203	else:
204	addr_nibbles = 0 # TODO: How to handle later on?
205
206	# Data is driven MSN-first.
207	offset = ((addr_nibbles - 1) - self.cur_nibble) * 4
208	self.addr \|= (lad << offset)
209
210	# Continue if we haven't seen all ADDR cycles, yet.
211	# TODO: Off-by-one?
212	if (self.cur_nibble < addr_nibbles - 1):
213	self.cur_nibble += 1
214	return
215
216	self.put(0, 0, self.out_ann, [0, ['Address: %s' % hex(self.addr)]])
217
218	self.state = 'GET TAR'
219	self.tar_count = 0
220
221	def handle_get_tar(self, lad, lad_bits):
222	# LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
223
224	self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s'
225	% (self.tarcount, lad_bits)]])
226
227	# On the first TAR clock cycle LAD[3:0] is driven to 1111 by
228	# either the host or peripheral. On the second clock cycle,
229	# the host or peripheral tri-states LAD[3:0], but its value
230	# should still be 1111, due to pull-ups on the LAD lines.
231	if lad_bits != '1111':
232	self.put(0, 0, self.out_ann,
233	[0, ['Warning: TAR, cycle %d: %s (expected 1111)'
234	% (self.tarcount, lad_bits)]])
235
236	if (self.tarcount != 2):
237	self.tarcount += 1
238	return
239
240	self.state = 'GET SYNC'
241
242	def handle_get_sync(self, lad, lad_bits):
243	# LAD[3:0]: SYNC field (1-n clock cycles).
244
245	self.sync_val = lad_bits
246	self.cycle_type = fields['SYNC'][lad]
247
248	# TODO: Warnings if reserved value are seen?
249	if self.cycle_type == 'Reserved':
250	self.put(0, 0, self.out_ann, [0, ['Warning: SYNC, cycle %d: %s '
251	'(reserved value)' % (self.synccount, self.sync_val)]])
252
253	self.put(0, 0, self.out_ann, [0, ['SYNC, cycle %d: %s'
254	% (self.synccount, self.sync_val)]])
255
256	# TODO
257
258	self.state = 'GET DATA'
259	self.cycle_count = 0
260
261	def handle_get_data(self, lad, lad_bits):
262	# LAD[3:0]: DATA field (2 clock cycles).
263
264	if (self.cycle_count == 0):
265	self.databyte = lad
266	elif (self.cycle_count == 1):
267	self.databyte \|= (lad << 4)
268	else:
269	pass # TODO: Error?
270
271	if (self.cycle_count != 2):
272	self.cycle_count += 1
273	return
274
275	self.put(0, 0, self.out_ann, [0, ['DATA: %s' % hex(self.databyte)]])
276
277	self.state = 'GET TAR2'
278
279	def handle_get_tar2(self, lad, lad_bits):
280	# LAD[3:0]: Second TAR field (2 clock cycles).
281
282	self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s'
283	% (self.tarcount, lad_bits)]])
284
285	# On the first TAR clock cycle LAD[3:0] is driven to 1111 by
286	# either the host or peripheral. On the second clock cycle,
287	# the host or peripheral tri-states LAD[3:0], but its value
288	# should still be 1111, due to pull-ups on the LAD lines.
289	if lad_bits != '1111':
290	self.put(0, 0, self.out_ann,
291	[0, ['Warning: TAR, cycle %d: %s (expected 1111)'
292	% (self.tarcount, lad_bits)]])
293
294	if (self.tarcount != 2):
295	self.tarcount += 1
296	return
297
298	self.state = 'GET SYNC'
299
300	# TODO: At which edge of the clock is data latched? Falling?
301	def decode(self, ss, es, data):
302	for (samplenum, pins) in data:
303
304	# If none of the pins changed, there's nothing to do.
305	if self.oldpins == pins:
306	continue
307
308	# Store current pin values for the next round.
309	self.oldpins = pins
310
311	# Get individual pin values into local variables.
312	# TODO: Handle optional pins.
313	(lframe, lreset, lclk, lad0, lad1, lad2, lad3) = pins
314
315	# Only look at the signals upon falling LCLK edges.
316	# TODO: Rising?
317	## if not (self.oldlclk == 1 and lclk == 0)
318	## self.oldlclk = lclk
319	## continue
320
321	# Store LAD[3:0] bit values (one nibble) in local variables.
2002229d	322	# Most (but not all) states need this.
271acd3b UH	323	if self.state != 'IDLE':
	324	lad = (lad3 << 3) \| (lad2 << 2) \| (lad1 << 1) \| lad0
	325	lad_bits = bin(lad)[2:]
	326
	327	# State machine
	328	if self.state == 'IDLE':
	329	# A valid LPC cycle starts with LFRAME# being asserted (low).
	330	# TODO?
	331	if lframe != 0:
	332	continue
	333	self.state = 'GET START'
	334	self.lad = -1
	335	# self.clocknum = 0
	336	elif self.state == 'GET START':
	337	handle_get_start(lad, lad_bits, lframe)
	338	elif self.state == 'GET CT/DR':
	339	handle_get_ct_dr(lad, lad_bits)
	340	elif self.state == 'GET ADDR':
	341	handle_get_addr(lad, lad_bits)
	342	elif self.state == 'GET TAR':
	343	handle_get_tar(lad, lad_bits)
	344	elif self.state == 'GET SYNC':
	345	handle_get_sync(lad, lad_bits)
	346	elif self.state == 'GET DATA':
	347	handle_get_data(lad, lad_bits)
	348	elif self.state == 'GET TAR2':
	349	handle_get_tar2(lad, lad_bits)
	350	else:
	351	raise Exception('Invalid state: %s' % self.state)
	352