[libsigrokdecode.git] / decoders / jitter / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# Helper dictionary for edge detection.
edge_detector = {
    'rising':  lambda x, y: bool(not x and y),
    'falling': lambda x, y: bool(x and not y),
    'both':    lambda x, y: bool(x ^ y),
}

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 2
    id = 'jitter'
    name = 'Jitter'
    longname = 'Timing jitter calculation'
    desc = 'Retrieves the timing jitter between two digital signals.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['jitter']
    channels = (
        {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
        {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
    )
    options = (
        {'id': 'clk_polarity', 'desc': 'Clock edge polarity',
            'default': 'rising', 'values': ('rising', 'falling', 'both')},
        {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
            'default': 'rising', 'values': ('rising', 'falling', 'both')},
    )
    annotations = (
        ('jitter', 'Jitter value'),
        ('clk_missed', 'Clock missed'),
        ('sig_missed', 'Signal missed'),
    )
    annotation_rows = (
        ('jitter', 'Jitter values', (0,)),
        ('clk_missed', 'Clock missed', (1,)),
        ('sig_missed', 'Signal missed', (2,)),
    )
    binary = (
        ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
    )

    def __init__(self, **kwargs):
        self.state = 'CLK'
        self.samplerate = None
        self.oldpin = None
        self.oldclk = self.oldsig = None
        self.clk_start = None
        self.sig_start = None
        self.clk_missed = 0
        self.sig_missed = 0

    def start(self):
        self.clk_edge = edge_detector[self.options['clk_polarity']]
        self.sig_edge = edge_detector[self.options['sig_polarity']]
        self.out_ann = self.register(srd.OUTPUT_ANN)
        self.out_bin = self.register(srd.OUTPUT_BINARY)
        self.out_clk_missed = self.register(srd.OUTPUT_META,
            meta=(int, 'Clock missed', 'Clock transition missed'))
        self.out_sig_missed = self.register(srd.OUTPUT_META,
            meta=(int, 'Signal missed', 'Resulting signal transition missed'))

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value

    # Helper function for jitter time annotations.
    def putx(self, delta):
        # Adjust granularity.
        if delta == 0 or delta >= 1:
            delta_s = u"%us" % (delta)
        elif delta <= 1e-12:
            delta_s = u"%.1ffs" % (delta * 1e15)
        elif delta <= 1e-9:
            delta_s = u"%.1fps" % (delta * 1e12)
        elif delta <= 1e-6:
            delta_s = u"%.1fns" % (delta * 1e9)
        elif delta <= 1e-3:
            delta_s = u"%.1fμs" % (delta * 1e6)
        else:
            delta_s = u"%.1fms" % (delta * 1e3)

        self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])

    # Helper function for ASCII float jitter values (one value per line).
    def putb(self, delta):
        if delta is None:
            return
        # Format the delta to an ASCII float output.
        for x in str(delta):
            self.put(self.clk_start, self.sig_start, self.out_bin, (0, bytes([ord(x)])))
        self.put(self.clk_start, self.sig_start, self.out_bin, (0, bytes([ord('\n')])))

    # Helper function for missed clock and signal annotations.
    def putm(self, data):
        self.put(self.samplenum, self.samplenum, self.out_ann, data)

    def handle_clk(self, clk, sig):
        if self.clk_start == self.samplenum:
            # Clock transition already treated.
            # We have done everything we can with this sample.
            return True

        if self.clk_edge(self.oldclk, clk):
            # Clock edge found.
            # We note the sample and move to the next state.
            self.clk_start = self.samplenum
            self.state = 'SIG'
            return False
        else:
            if self.sig_start is not None \
               and self.sig_start != self.samplenum \
               and self.sig_edge(self.oldsig, sig):
                # If any transition in the resulting signal
                # occurs while we are waiting for a clock,
                # we increase the missed signal counter.
                self.sig_missed += 1
                self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
                self.putm([2, ['Missed signal', 'MS']])
            # No clock edge found, we have done everything we
            # can with this sample.
            return True

    def handle_sig(self, clk, sig):
        if self.sig_start == self.samplenum:
            # Signal transition already treated.
            # We have done everything we can with this sample.
            return True

        if self.sig_edge(self.oldsig, sig):
            # Signal edge found.
            # We note the sample, calculate the jitter
            # and move to the next state.
            self.sig_start = self.samplenum
            self.state = 'CLK'
            # Calculate and report the timing jitter.
            delta = (self.sig_start - self.clk_start) / self.samplerate
            self.putx(delta)
            self.putb(delta)
            return False
        else:
            if self.clk_start != self.samplenum \
               and self.clk_edge(self.oldclk, clk):
                # If any transition in the clock signal
                # occurs while we are waiting for a resulting
                # signal, we increase the missed clock counter.
                self.clk_missed += 1
                self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
                self.putm([1, ['Missed clock', 'MC']])
            # No resulting signal edge found, we have done
            # everything we can with this sample.
            return True

    def decode(self, ss, es, data):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')

        for (self.samplenum, pins) in data:
            # We are only interested in transitions.
            if self.oldpin == pins:
                continue

            self.oldpin, (clk, sig) = pins, pins

            if self.oldclk is None and self.oldsig is None:
                self.oldclk, self.oldsig = clk, sig

            # State machine:
            # For each sample we can move 2 steps forward in the state machine.
            while True:
                # Clock state has the lead.
                if self.state == 'CLK':
                    if self.handle_clk(clk, sig):
                        break
                if self.state == 'SIG':
                    if self.handle_sig(clk, sig):
                        break

            # Save current CLK/SIG values for the next round.
            self.oldclk, self.oldsig = clk, sig
Commit	Line	Data
c2049e2c SB	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22
	23	# Helper dictionary for edge detection.
	24	edge_detector = {
	25	'rising': lambda x, y: bool(not x and y),
	26	'falling': lambda x, y: bool(x and not y),
	27	'both': lambda x, y: bool(x ^ y),
	28	}
	29
	30	class SamplerateError(Exception):
	31	pass
	32
	33	class Decoder(srd.Decoder):
	34	api_version = 2
	35	id = 'jitter'
	36	name = 'Jitter'
	37	longname = 'Timing jitter calculation'
	38	desc = 'Retrieves the timing jitter between two digital signals.'
	39	license = 'gplv2+'
	40	inputs = ['logic']
	41	outputs = ['jitter']
	42	channels = (
	43	{'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
	44	{'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
	45	)
	46	options = (
	47	{'id': 'clk_polarity', 'desc': 'Clock edge polarity',
	48	'default': 'rising', 'values': ('rising', 'falling', 'both')},
	49	{'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
	50	'default': 'rising', 'values': ('rising', 'falling', 'both')},
	51	)
	52	annotations = (
	53	('jitter', 'Jitter value'),
	54	('clk_missed', 'Clock missed'),
	55	('sig_missed', 'Signal missed'),
	56	)
	57	annotation_rows = (
	58	('jitter', 'Jitter values', (0,)),
	59	('clk_missed', 'Clock missed', (1,)),
	60	('sig_missed', 'Signal missed', (2,)),
	61	)
5f987d6f	62	binary = (
05aaa486	63	('ascii-float', 'Jitter values as newline-separated ASCII floats'),
5f987d6f	64	)
c2049e2c SB	65
	66	def __init__(self, **kwargs):
	67	self.state = 'CLK'
	68	self.samplerate = None
	69	self.oldpin = None
	70	self.oldclk = self.oldsig = None
	71	self.clk_start = None
	72	self.sig_start = None
	73	self.clk_missed = 0
	74	self.sig_missed = 0
	75
	76	def start(self):
	77	self.clk_edge = edge_detector[self.options['clk_polarity']]
	78	self.sig_edge = edge_detector[self.options['sig_polarity']]
	79	self.out_ann = self.register(srd.OUTPUT_ANN)
5f987d6f	80	self.out_bin = self.register(srd.OUTPUT_BINARY)
c2049e2c SB	81	self.out_clk_missed = self.register(srd.OUTPUT_META,
	82	meta=(int, 'Clock missed', 'Clock transition missed'))
	83	self.out_sig_missed = self.register(srd.OUTPUT_META,
	84	meta=(int, 'Signal missed', 'Resulting signal transition missed'))
	85
	86	def metadata(self, key, value):
	87	if key == srd.SRD_CONF_SAMPLERATE:
	88	self.samplerate = value
	89
	90	# Helper function for jitter time annotations.
	91	def putx(self, delta):
	92	# Adjust granularity.
	93	if delta == 0 or delta >= 1:
	94	delta_s = u"%us" % (delta)
	95	elif delta <= 1e-12:
	96	delta_s = u"%.1ffs" % (delta * 1e15)
	97	elif delta <= 1e-9:
	98	delta_s = u"%.1fps" % (delta * 1e12)
	99	elif delta <= 1e-6:
	100	delta_s = u"%.1fns" % (delta * 1e9)
	101	elif delta <= 1e-3:
	102	delta_s = u"%.1fμs" % (delta * 1e6)
	103	else:
	104	delta_s = u"%.1fms" % (delta * 1e3)
	105
	106	self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
	107
05aaa486	108	# Helper function for ASCII float jitter values (one value per line).
5f987d6f SB	109	def putb(self, delta):
	110	if delta is None:
	111	return
05aaa486	112	# Format the delta to an ASCII float output.
5f987d6f SB	113	for x in str(delta):
	114	self.put(self.clk_start, self.sig_start, self.out_bin, (0, bytes([ord(x)])))
	115	self.put(self.clk_start, self.sig_start, self.out_bin, (0, bytes([ord('\n')])))
	116
c2049e2c SB	117	# Helper function for missed clock and signal annotations.
	118	def putm(self, data):
	119	self.put(self.samplenum, self.samplenum, self.out_ann, data)
	120
34cfd419 UH	121	def handle_clk(self, clk, sig):
	122	if self.clk_start == self.samplenum:
	123	# Clock transition already treated.
	124	# We have done everything we can with this sample.
	125	return True
	126
	127	if self.clk_edge(self.oldclk, clk):
	128	# Clock edge found.
	129	# We note the sample and move to the next state.
	130	self.clk_start = self.samplenum
	131	self.state = 'SIG'
	132	return False
	133	else:
	134	if self.sig_start is not None \
	135	and self.sig_start != self.samplenum \
	136	and self.sig_edge(self.oldsig, sig):
	137	# If any transition in the resulting signal
	138	# occurs while we are waiting for a clock,
	139	# we increase the missed signal counter.
	140	self.sig_missed += 1
961699aa	141	self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
34cfd419 UH	142	self.putm([2, ['Missed signal', 'MS']])
	143	# No clock edge found, we have done everything we
	144	# can with this sample.
	145	return True
	146
	147	def handle_sig(self, clk, sig):
	148	if self.sig_start == self.samplenum:
	149	# Signal transition already treated.
	150	# We have done everything we can with this sample.
	151	return True
	152
	153	if self.sig_edge(self.oldsig, sig):
	154	# Signal edge found.
	155	# We note the sample, calculate the jitter
	156	# and move to the next state.
	157	self.sig_start = self.samplenum
	158	self.state = 'CLK'
	159	# Calculate and report the timing jitter.
5f987d6f SB	160	delta = (self.sig_start - self.clk_start) / self.samplerate
	161	self.putx(delta)
	162	self.putb(delta)
34cfd419 UH	163	return False
	164	else:
	165	if self.clk_start != self.samplenum \
	166	and self.clk_edge(self.oldclk, clk):
	167	# If any transition in the clock signal
	168	# occurs while we are waiting for a resulting
	169	# signal, we increase the missed clock counter.
	170	self.clk_missed += 1
961699aa	171	self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
34cfd419 UH	172	self.putm([1, ['Missed clock', 'MC']])
	173	# No resulting signal edge found, we have done
	174	# everything we can with this sample.
	175	return True
	176
c2049e2c SB	177	def decode(self, ss, es, data):
	178	if not self.samplerate:
	179	raise SamplerateError('Cannot decode without samplerate.')
	180
	181	for (self.samplenum, pins) in data:
	182	# We are only interested in transitions.
	183	if self.oldpin == pins:
	184	continue
	185
	186	self.oldpin, (clk, sig) = pins, pins
	187
	188	if self.oldclk is None and self.oldsig is None:
	189	self.oldclk, self.oldsig = clk, sig
	190
	191	# State machine:
	192	# For each sample we can move 2 steps forward in the state machine.
	193	while True:
c2049e2c SB	194	# Clock state has the lead.
c2049e2c SB	195	if self.state == 'CLK':
34cfd419	196	if self.handle_clk(clk, sig):
c2049e2c	197	break
c2049e2c	198	if self.state == 'SIG':
34cfd419	199	if self.handle_sig(clk, sig):
c2049e2c	200	break
c2049e2c SB	201
	202	# Save current CLK/SIG values for the next round.
	203	self.oldclk, self.oldsig = clk, sig