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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2017 Marcus Comstedt <marcus@mc.pp.se>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, see <http://www.gnu.org/licenses/>.
18##
19
20import sigrokdecode as srd
21
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22step_wait_conds = (
23 [{2: 'f'}, {0: 'l', 1: 'h'}],
24 [{2: 'f'}, {0: 'h', 1: 'h'}, {1: 'l'}],
25 [{2: 'f'}, {0: 'f'}, {1: 'l'}],
26 [{2: 'f'}, {1: 'e'}],
27)
28
a92df5ba 29class Decoder(srd.Decoder):
483f2aff 30 api_version = 3
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31 id = 'iec'
32 name = 'IEC'
33 longname = 'Commodore bus'
34 desc = 'Commodore serial IEEE-488 (IEC) bus protocol.'
35 license = 'gplv2+'
36 inputs = ['logic']
37 outputs = ['gpib']
d6d8a8a4 38 tags = ['PC', 'Retro computing']
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39 channels = (
40 {'id': 'data', 'name': 'DATA', 'desc': 'Data I/O'},
41 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
42 {'id': 'atn', 'name': 'ATN', 'desc': 'Attention'},
43 )
44 optional_channels = (
45 {'id': 'srq', 'name': 'SRQ', 'desc': 'Service request'},
46 )
47 annotations = (
48 ('items', 'Items'),
49 ('gpib', 'DAT/CMD'),
50 ('eoi', 'EOI'),
51 )
52 annotation_rows = (
53 ('bytes', 'Bytes', (0,)),
54 ('gpib', 'DAT/CMD', (1,)),
55 ('eoi', 'EOI', (2,)),
56 )
57
58 def __init__(self):
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59 self.reset()
60
61 def reset(self):
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62 self.saved_ATN = False
63 self.saved_EOI = False
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64 self.ss_item = self.es_item = None
65 self.step = 0
66 self.bits = 0
67 self.numbits = 0
68
69 def start(self):
70 self.out_ann = self.register(srd.OUTPUT_ANN)
71
72 def putb(self, data):
73 self.put(self.ss_item, self.es_item, self.out_ann, data)
74
75 def handle_bits(self):
76 # Output the saved item.
77 dbyte = self.bits
78 dATN = self.saved_ATN
79 dEOI = self.saved_EOI
80 self.es_item = self.samplenum
81 self.putb([0, ['%02X' % dbyte]])
82
83 # Encode item byte to GPIB convention.
84 self.strgpib = ' '
85 if dATN: # ATN, decode commands.
86 # Note: Commands < 0x20 are not used on IEC bus.
87 if dbyte == 0x01: self.strgpib = 'GTL'
88 if dbyte == 0x04: self.strgpib = 'SDC'
89 if dbyte == 0x05: self.strgpib = 'PPC'
90 if dbyte == 0x08: self.strgpib = 'GET'
91 if dbyte == 0x09: self.strgpib = 'TCT'
92 if dbyte == 0x11: self.strgpib = 'LLO'
93 if dbyte == 0x14: self.strgpib = 'DCL'
94 if dbyte == 0x15: self.strgpib = 'PPU'
95 if dbyte == 0x18: self.strgpib = 'SPE'
96 if dbyte == 0x19: self.strgpib = 'SPD'
97
98 if dbyte == 0x3f: self.strgpib = 'UNL'
99 if dbyte == 0x5f: self.strgpib = 'UNT'
100 if dbyte > 0x1f and dbyte < 0x3f: # Address listener.
101 self.strgpib = 'L' + chr(dbyte + 0x10)
102 if dbyte > 0x3f and dbyte < 0x5f: # Address talker.
103 self.strgpib = 'T' + chr(dbyte - 0x10)
104 if dbyte > 0x5f and dbyte < 0x70: # Channel reopen.
105 self.strgpib = 'R' + chr(dbyte - 0x30)
106 if dbyte > 0xdf and dbyte < 0xf0: # Channel close.
107 self.strgpib = 'C' + chr(dbyte - 0xb0)
108 if dbyte > 0xef: # Channel open.
109 self.strgpib = 'O' + chr(dbyte - 0xc0)
110 else:
111 if dbyte > 0x1f and dbyte < 0x7f:
112 self.strgpib = chr(dbyte)
113 if dbyte == 0x0a:
114 self.strgpib = 'LF'
115 if dbyte == 0x0d:
116 self.strgpib = 'CR'
117
118 self.putb([1, [self.strgpib]])
119 self.strEOI = ' '
120 if dEOI:
121 self.strEOI = 'EOI'
122 self.putb([2, [self.strEOI]])
123
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124 def decode(self):
125 while True:
a92df5ba 126
483f2aff 127 data, clk, atn, srq = self.wait(step_wait_conds[self.step])
a92df5ba 128
483f2aff 129 if self.matched[0]:
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130 # Falling edge on ATN, reset step.
131 self.step = 0
132
133 if self.step == 0:
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134 # Don't use self.matched[1] here since we might come from
135 # a step with different conds due to the code above.
136 if data == 0 and clk == 1:
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137 # Rising edge on CLK while DATA is low: Ready to send.
138 self.step = 1
139 elif self.step == 1:
483f2aff 140 if data == 1 and clk == 1:
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141 # Rising edge on DATA while CLK is high: Ready for data.
142 self.ss_item = self.samplenum
483f2aff 143 self.saved_ATN = not atn
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144 self.saved_EOI = False
145 self.bits = 0
146 self.numbits = 0
147 self.step = 2
483f2aff 148 elif clk == 0:
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149 # CLK low again, transfer aborted.
150 self.step = 0
151 elif self.step == 2:
483f2aff 152 if data == 0 and clk == 1:
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153 # DATA goes low while CLK is still high, EOI confirmed.
154 self.saved_EOI = True
483f2aff 155 elif clk == 0:
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156 self.step = 3
157 elif self.step == 3:
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158 if self.matched[1]:
159 if clk == 1:
160 # Rising edge on CLK; latch DATA.
161 self.bits |= data << self.numbits
162 elif clk == 0:
163 # Falling edge on CLK; end of bit.
164 self.numbits += 1
165 if self.numbits == 8:
166 self.handle_bits()
167 self.step = 0