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1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2017 Marcus Comstedt <marcus@mc.pp.se> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | ||
22 | class Decoder(srd.Decoder): | |
23 | api_version = 2 | |
24 | id = 'iec' | |
25 | name = 'IEC' | |
26 | longname = 'Commodore bus' | |
27 | desc = 'Commodore serial IEEE-488 (IEC) bus protocol.' | |
28 | license = 'gplv2+' | |
29 | inputs = ['logic'] | |
30 | outputs = ['gpib'] | |
31 | channels = ( | |
32 | {'id': 'data', 'name': 'DATA', 'desc': 'Data I/O'}, | |
33 | {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, | |
34 | {'id': 'atn', 'name': 'ATN', 'desc': 'Attention'}, | |
35 | ) | |
36 | optional_channels = ( | |
37 | {'id': 'srq', 'name': 'SRQ', 'desc': 'Service request'}, | |
38 | ) | |
39 | annotations = ( | |
40 | ('items', 'Items'), | |
41 | ('gpib', 'DAT/CMD'), | |
42 | ('eoi', 'EOI'), | |
43 | ) | |
44 | annotation_rows = ( | |
45 | ('bytes', 'Bytes', (0,)), | |
46 | ('gpib', 'DAT/CMD', (1,)), | |
47 | ('eoi', 'EOI', (2,)), | |
48 | ) | |
49 | ||
50 | def __init__(self): | |
51 | self.saved_ATN = False | |
52 | self.saved_EOI = False | |
53 | self.oldpins = None | |
54 | self.ss_item = self.es_item = None | |
55 | self.step = 0 | |
56 | self.bits = 0 | |
57 | self.numbits = 0 | |
58 | ||
59 | def start(self): | |
60 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
61 | ||
62 | def putb(self, data): | |
63 | self.put(self.ss_item, self.es_item, self.out_ann, data) | |
64 | ||
65 | def handle_bits(self): | |
66 | # Output the saved item. | |
67 | dbyte = self.bits | |
68 | dATN = self.saved_ATN | |
69 | dEOI = self.saved_EOI | |
70 | self.es_item = self.samplenum | |
71 | self.putb([0, ['%02X' % dbyte]]) | |
72 | ||
73 | # Encode item byte to GPIB convention. | |
74 | self.strgpib = ' ' | |
75 | if dATN: # ATN, decode commands. | |
76 | # Note: Commands < 0x20 are not used on IEC bus. | |
77 | if dbyte == 0x01: self.strgpib = 'GTL' | |
78 | if dbyte == 0x04: self.strgpib = 'SDC' | |
79 | if dbyte == 0x05: self.strgpib = 'PPC' | |
80 | if dbyte == 0x08: self.strgpib = 'GET' | |
81 | if dbyte == 0x09: self.strgpib = 'TCT' | |
82 | if dbyte == 0x11: self.strgpib = 'LLO' | |
83 | if dbyte == 0x14: self.strgpib = 'DCL' | |
84 | if dbyte == 0x15: self.strgpib = 'PPU' | |
85 | if dbyte == 0x18: self.strgpib = 'SPE' | |
86 | if dbyte == 0x19: self.strgpib = 'SPD' | |
87 | ||
88 | if dbyte == 0x3f: self.strgpib = 'UNL' | |
89 | if dbyte == 0x5f: self.strgpib = 'UNT' | |
90 | if dbyte > 0x1f and dbyte < 0x3f: # Address listener. | |
91 | self.strgpib = 'L' + chr(dbyte + 0x10) | |
92 | if dbyte > 0x3f and dbyte < 0x5f: # Address talker. | |
93 | self.strgpib = 'T' + chr(dbyte - 0x10) | |
94 | if dbyte > 0x5f and dbyte < 0x70: # Channel reopen. | |
95 | self.strgpib = 'R' + chr(dbyte - 0x30) | |
96 | if dbyte > 0xdf and dbyte < 0xf0: # Channel close. | |
97 | self.strgpib = 'C' + chr(dbyte - 0xb0) | |
98 | if dbyte > 0xef: # Channel open. | |
99 | self.strgpib = 'O' + chr(dbyte - 0xc0) | |
100 | else: | |
101 | if dbyte > 0x1f and dbyte < 0x7f: | |
102 | self.strgpib = chr(dbyte) | |
103 | if dbyte == 0x0a: | |
104 | self.strgpib = 'LF' | |
105 | if dbyte == 0x0d: | |
106 | self.strgpib = 'CR' | |
107 | ||
108 | self.putb([1, [self.strgpib]]) | |
109 | self.strEOI = ' ' | |
110 | if dEOI: | |
111 | self.strEOI = 'EOI' | |
112 | self.putb([2, [self.strEOI]]) | |
113 | ||
114 | def decode(self, ss, es, data): | |
115 | for (self.samplenum, pins) in data: | |
116 | ||
117 | # Ignore identical samples early on (for performance reasons). | |
118 | if self.oldpins == pins: | |
119 | continue | |
120 | ||
121 | if pins[2] == 0 and self.oldpins[2] == 1: | |
122 | # Falling edge on ATN, reset step. | |
123 | self.step = 0 | |
124 | ||
125 | if self.step == 0: | |
126 | if pins[0] == 0 and pins[1] == 1: | |
127 | # Rising edge on CLK while DATA is low: Ready to send. | |
128 | self.step = 1 | |
129 | elif self.step == 1: | |
130 | if pins[0] == 1 and pins[1] == 1: | |
131 | # Rising edge on DATA while CLK is high: Ready for data. | |
132 | self.ss_item = self.samplenum | |
133 | self.saved_ATN = not pins[2] | |
134 | self.saved_EOI = False | |
135 | self.bits = 0 | |
136 | self.numbits = 0 | |
137 | self.step = 2 | |
138 | elif pins[1] == 0: | |
139 | # CLK low again, transfer aborted. | |
140 | self.step = 0 | |
141 | elif self.step == 2: | |
142 | if pins[0] == 0 and pins[1] == 1: | |
143 | # DATA goes low while CLK is still high, EOI confirmed. | |
144 | self.saved_EOI = True | |
145 | elif pins[1] == 0: | |
146 | self.step = 3 | |
147 | elif self.step == 3: | |
148 | if pins[1] == 1 and self.oldpins[1] == 0: | |
149 | # Rising edge on CLK; latch DATA. | |
150 | self.bits |= pins[0] << self.numbits | |
151 | elif pins[1] == 0 and self.oldpins[1] == 1: | |
152 | # Falling edge on CLK; end of bit. | |
153 | self.numbits += 1 | |
154 | if self.numbits == 8: | |
155 | self.handle_bits() | |
156 | self.step = 0 | |
157 | ||
158 | self.oldpins = pins |