projects / libsigrokdecode.git / blame
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| 64c29e28 UH |
1 | ## |
| 2 | ## This file is part of the sigrok project. | |
| 3 | ## | |
| 4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
| 5 | ## | |
| 6 | ## This program is free software; you can redistribute it and/or modify | |
| 7 | ## it under the terms of the GNU General Public License as published by | |
| 8 | ## the Free Software Foundation; either version 2 of the License, or | |
| 9 | ## (at your option) any later version. | |
| 10 | ## | |
| 11 | ## This program is distributed in the hope that it will be useful, | |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | ## GNU General Public License for more details. | |
| 15 | ## | |
| 16 | ## You should have received a copy of the GNU General Public License | |
| 17 | ## along with this program; if not, write to the Free Software | |
| 18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 19 | ## | |
| 20 | ||
| 156509ca UH |
21 | ''' |
| 22 | I2C protocol decoder. | |
| 23 | ||
| 24 | The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master | |
| 25 | bus using two signals (SCL = serial clock line, SDA = serial data line). | |
| 26 | ||
| 27 | There can be many devices on the same bus. Each device can potentially be | |
| 28 | master or slave (and that can change during runtime). Both slave and master | |
| 29 | can potentially play the transmitter or receiver role (this can also | |
| 30 | change at runtime). | |
| 31 | ||
| 32 | Possible maximum data rates: | |
| 33 | - Standard mode: 100 kbit/s | |
| 34 | - Fast mode: 400 kbit/s | |
| 35 | - Fast-mode Plus: 1 Mbit/s | |
| 36 | - High-speed mode: 3.4 Mbit/s | |
| 37 | ||
| 38 | START condition (S): SDA = falling, SCL = high | |
| 39 | Repeated START condition (Sr): same as S | |
| 40 | Data bit sampling: SCL = rising | |
| 41 | STOP condition (P): SDA = rising, SCL = high | |
| 42 | ||
| 43 | All data bytes on SDA are exactly 8 bits long (transmitted MSB-first). | |
| 44 | Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low, | |
| 45 | that indicates an ACK, if it's high that indicates a NACK. | |
| 46 | ||
| 47 | After the first START condition, a master sends the device address of the | |
| 48 | slave it wants to talk to. Slave addresses are 7 bits long (MSB-first). | |
| 49 | After those 7 bits, a data direction bit is sent. If the bit is low that | |
| 50 | indicates a WRITE operation, if it's high that indicates a READ operation. | |
| 51 | ||
| 52 | Later an optional 10bit slave addressing scheme was added. | |
| 53 | ||
| 54 | Documentation: | |
| 55 | http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec) | |
| 56 | http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec) | |
| 57 | http://en.wikipedia.org/wiki/I2C | |
| 58 | ||
| 59 | Protocol output format: | |
| 60 | ||
| 61 | I2C packet: | |
| f9d87f64 | 62 | [<cmd>, <data>] |
| 156509ca | 63 | |
| f9d87f64 | 64 | <cmd> is one of: |
| 71077f34 UH |
65 | - 'START' (START condition) |
| 66 | - 'START REPEAT' (Repeated START condition) | |
| 67 | - 'ADDRESS READ' (Slave address, read) | |
| 68 | - 'ADDRESS WRITE' (Slave address, write) | |
| 69 | - 'DATA READ' (Data, read) | |
| 70 | - 'DATA WRITE' (Data, write) | |
| 71 | - 'STOP' (STOP condition) | |
| 72 | - 'ACK' (ACK bit) | |
| 73 | - 'NACK' (NACK bit) | |
| 156509ca UH |
74 | |
| 75 | <data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*' | |
| f9d87f64 UH |
76 | command. Slave addresses do not include bit 0 (the READ/WRITE indication bit). |
| 77 | For example, a slave address field could be 0x51 (instead of 0xa2). | |
| 78 | For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None. | |
| 156509ca | 79 | |
| 156509ca UH |
80 | ''' |
| 81 | ||
| 64c29e28 UH |
82 | from .i2c import * |
| 83 |