[libsigrokdecode.git] / decoders / i2c.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

#
# I2C protocol decoder
#

#
# The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
# bus using two signals (SCL = serial clock line, SDA = serial data line).
#
# There can be many devices on the same bus. Each device can potentially be
# master or slave (and that can change during runtime). Both slave and master
# can potentially play the transmitter or receiver role (this can also
# change at runtime).
#
# Possible maximum data rates:
#  - Standard mode: 100 kbit/s
#  - Fast mode: 400 kbit/s
#  - Fast-mode Plus: 1 Mbit/s
#  - High-speed mode: 3.4 Mbit/s
#
# START condition (S): SDA = falling, SCL = high
# Repeated START condition (Sr): same as S
# STOP condition (P): SDA = rising, SCL = high
#
# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
# Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
# that indicates an ACK, if it's high that indicates a NACK.
#
# After the first START condition, a master sends the device address of the
# slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
# After those 7 bits, a data direction bit is sent. If the bit is low that
# indicates a WRITE operation, if it's high that indicates a READ operation.
#
# Later an optional 10bit slave addressing scheme was added.
#
# Documentation:
# http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
# http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
# http://en.wikipedia.org/wiki/I2C
#

# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
# TODO: Handle clock stretching.
# TODO: Handle combined messages / repeated START.
# TODO: Implement support for 7bit and 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.

#
# I2C output format:
#
# The output consists of a (Python) list of I2C "packets", each of which
# has an (implicit) index number (its index in the list).
# Each packet consists of a Python dict with certain key/value pairs.
#
# TODO: Make this a list later instead of a dict?
#
# 'type': (string)
#   - 'S' (START condition)
#   - 'Sr' (Repeated START)
#   - 'AR' (Address, read)
#   - 'AW' (Address, write)
#   - 'DR' (Data, read)
#   - 'DW' (Data, write)
#   - 'P' (STOP condition)
# 'range': (tuple of 2 integers, the min/max samplenumber of this range)
#   - (min, max)
#   - min/max can also be identical.
# 'data': (actual data as integer ???) TODO: This can be very variable...
# 'ann': (string; additional annotations / comments)
#
# Example output:
# [{'type': 'S',  'range': (150, 160), 'data': None, 'ann': 'Foobar'},
#  {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'},
#  {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'},
#  {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'},
#  {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'},
#  {'type': 'P',  'range': (650, 660), 'data': None, 'ann': None}]
#
# Possible other events:
#   - Error event in case protocol looks broken:
#     [{'type': 'ERROR', 'range': (min, max),
#	'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
#     [{'type': 'ERROR', 'range': (min, max),
#	'data': TODO, 'ann': 'TODO'},
#   - TODO: Make list of possible errors accessible as metadata?
#
# TODO: I2C address of slaves.
# TODO: Handle multiple different I2C devices on same bus
#       -> we need to decode multiple protocols at the same time.
# TODO: range: Always contiguous? Splitted ranges? Multiple per event?
#

#
# I2C input format:
#
# signals:
# [[id, channel, description], ...] # TODO
#
# Example:
# {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'}
# {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'}
# ...
#
# {'inbuf': [...],
#  'signals': [{'SCL': }]}
#

def decode(l):
	print(l)
	sigrok.put(l)


def decode2(inbuf):
	"""I2C protocol decoder"""

	# FIXME: Get the data in the correct format in the first place.
	inbuf = [ord(x) for x in inbuf]

	# FIXME: This should be passed in as metadata, not hardcoded here.
	metadata = {
	  'numchannels': 8,
	  'signals': {
	      'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'},
	      'sda': {'ch': 7, 'name': 'SDA', 'desc': 'Serial data line'},
	    },
	}

	out = []
	o = ack = d = ''
	bitcount = data = 0
	wr = startsample = -1
	IDLE, START, ADDRESS, DATA = range(4)
	state = IDLE

	# Get the channel/probe number of the SCL/SDA signals.
	scl_bit = metadata['signals']['scl']['ch']
	sda_bit = metadata['signals']['sda']['ch']

	# Get SCL/SDA bit values (0/1 for low/high) of the first sample.
	s = inbuf[0]
	oldscl = (s & (1 << scl_bit)) >> scl_bit
	oldsda = (s & (1 << sda_bit)) >> sda_bit

	# Loop over all samples.
	# TODO: Handle LAs with more/less than 8 channels.
	for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
		# Get SCL/SDA bit values (0/1 for low/high).
		scl = (s & (1 << scl_bit)) >> scl_bit
		sda = (s & (1 << sda_bit)) >> sda_bit

		# TODO: Wait until the bus is idle (SDA = SCL = 1) first?

		# START condition (S): SDA = falling, SCL = high
		if (oldsda == 1 and sda == 0) and scl == 1:
			o = {'type': 'S', 'range': (samplenum, samplenum),
			     'data': None, 'ann': None},
			out.append(o)
			state = ADDRESS
			bitcount = data = 0

		# Data latching by transmitter: SCL = low
		elif (scl == 0):
			pass # TODO

		# Data sampling of receiver: SCL = rising
		elif (oldscl == 0 and scl == 1):
			if startsample == -1:
				startsample = samplenum
			bitcount += 1

			# out.append("%d\t\tRECEIVED BIT %d:  %d\n" % \
			# 	(samplenum, 8 - bitcount, sda))

			# Address and data are transmitted MSB-first.
			data <<= 1
			data |= sda

			if bitcount != 9:
				continue

			# We received 8 address/data bits and the ACK/NACK bit.
			data >>= 1 # Shift out unwanted ACK/NACK bit here.
			ack = (sda == 1) and 'N' or 'A'
			d = (state == ADDRESS) and (data & 0xfe) or data
			if state == ADDRESS:
				wr = (data & 1) and 1 or 0
				state = DATA
			o = {'type': state,
			     'range': (startsample, samplenum - 1),
			     'data': d, 'ann': None}
			if state == ADDRESS and wr == 1:
				o['type'] = 'AW'
			elif state == ADDRESS and wr == 0:
				o['type'] = 'AR'
			elif state == DATA and wr == 1:
				o['type'] = 'DW'
			elif state == DATA and wr == 0:
				o['type'] = 'DR'
			out.append(o)
			o = {'type': ack, 'range': (samplenum, samplenum),
			     'data': None, 'ann': None}
			out.append(o)
			bitcount = data = startsample = 0
			startsample = -1

		# STOP condition (P): SDA = rising, SCL = high
		elif (oldsda == 0 and sda == 1) and scl == 1:
			o = {'type': 'P', 'range': (samplenum, samplenum),
			     'data': None, 'ann': None},
			out.append(o)
			state = IDLE
			wr = -1

		# Save current SDA/SCL values for the next round.
		oldscl = scl
		oldsda = sda

	# FIXME: Just for testing...
	return str(out)

register = {
	'id': 'i2c',
	'name': 'I2C',
	'longname': 'Inter-Integrated Circuit (I2C) bus',
	'desc': 'I2C is a two-wire, multi-master, serial bus.',
	'longdesc': '...',
	'author': 'Uwe Hermann',
	'email': 'uwe@hermann-uwe.de',
	'license': 'gplv2+',
	'in': ['logic'],
	'out': ['i2c'],
	'probes': [
		['scl', 'Serial clock line'],
		['sda', 'Serial data line'],
	],
	'options': {
		'address-space': ['Address space (in bits)', 7],
	},
	# 'start': start,
	# 'report': report,
}

# Use psyco (if available) as it results in huge performance improvements.
try:
	import psyco
	psyco.bind(decode)
except ImportError:
	pass
Commit	Line	Data
0588ed70 UH	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	#
	22	# I2C protocol decoder
	23	#
	24
	25	#
	26	# The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
	27	# bus using two signals (SCL = serial clock line, SDA = serial data line).
	28	#
	29	# There can be many devices on the same bus. Each device can potentially be
	30	# master or slave (and that can change during runtime). Both slave and master
	31	# can potentially play the transmitter or receiver role (this can also
	32	# change at runtime).
	33	#
	34	# Possible maximum data rates:
	35	# - Standard mode: 100 kbit/s
	36	# - Fast mode: 400 kbit/s
	37	# - Fast-mode Plus: 1 Mbit/s
	38	# - High-speed mode: 3.4 Mbit/s
	39	#
	40	# START condition (S): SDA = falling, SCL = high
	41	# Repeated START condition (Sr): same as S
	42	# STOP condition (P): SDA = rising, SCL = high
	43	#
33e72c54	44	# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
0588ed70 UH	45	# Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
	46	# that indicates an ACK, if it's high that indicates a NACK.
	47	#
	48	# After the first START condition, a master sends the device address of the
	49	# slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
33e72c54	50	# After those 7 bits, a data direction bit is sent. If the bit is low that
0588ed70 UH	51	# indicates a WRITE operation, if it's high that indicates a READ operation.
	52	#
	53	# Later an optional 10bit slave addressing scheme was added.
	54	#
	55	# Documentation:
	56	# http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
	57	# http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
	58	# http://en.wikipedia.org/wiki/I2C
	59	#
	60
	61	# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
	62	# TODO: Handle clock stretching.
	63	# TODO: Handle combined messages / repeated START.
	64	# TODO: Implement support for 7bit and 10bit slave addresses.
	65	# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
	66	# TODO: Implement support for detecting various bus errors.
	67
23fb2e12 UH	68	#
	69	# I2C output format:
	70	#
	71	# The output consists of a (Python) list of I2C "packets", each of which
	72	# has an (implicit) index number (its index in the list).
	73	# Each packet consists of a Python dict with certain key/value pairs.
	74	#
	75	# TODO: Make this a list later instead of a dict?
	76	#
	77	# 'type': (string)
	78	# - 'S' (START condition)
	79	# - 'Sr' (Repeated START)
	80	# - 'AR' (Address, read)
	81	# - 'AW' (Address, write)
	82	# - 'DR' (Data, read)
	83	# - 'DW' (Data, write)
	84	# - 'P' (STOP condition)
	85	# 'range': (tuple of 2 integers, the min/max samplenumber of this range)
	86	# - (min, max)
	87	# - min/max can also be identical.
	88	# 'data': (actual data as integer ???) TODO: This can be very variable...
	89	# 'ann': (string; additional annotations / comments)
	90	#
	91	# Example output:
	92	# [{'type': 'S', 'range': (150, 160), 'data': None, 'ann': 'Foobar'},
	93	# {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'},
	94	# {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'},
	95	# {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'},
	96	# {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'},
	97	# {'type': 'P', 'range': (650, 660), 'data': None, 'ann': None}]
	98	#
	99	# Possible other events:
	100	# - Error event in case protocol looks broken:
	101	# [{'type': 'ERROR', 'range': (min, max),
	102	# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
	103	# [{'type': 'ERROR', 'range': (min, max),
	104	# 'data': TODO, 'ann': 'TODO'},
	105	# - TODO: Make list of possible errors accessible as metadata?
	106	#
	107	# TODO: I2C address of slaves.
	108	# TODO: Handle multiple different I2C devices on same bus
	109	# -> we need to decode multiple protocols at the same time.
	110	# TODO: range: Always contiguous? Splitted ranges? Multiple per event?
	111	#
	112
	113	#
	114	# I2C input format:
	115	#
	116	# signals:
	117	# [[id, channel, description], ...] # TODO
	118	#
	119	# Example:
	120	# {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'}
	121	# {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'}
	122	# ...
	123	#
	124	# {'inbuf': [...],
	125	# 'signals': [{'SCL': }]}
	126	#
	127
922763ab KS	128	def decode(l):
	129	print(l)
	130	sigrok.put(l)
	131
	132
	133
	134	def decode2(inbuf):
0588ed70 UH	135	"""I2C protocol decoder"""
0588ed70 UH	136
a156f09e UH	137	# FIXME: Get the data in the correct format in the first place.
	138	inbuf = [ord(x) for x in inbuf]
	139
0588ed70	140	# FIXME: This should be passed in as metadata, not hardcoded here.
23fb2e12 UH	141	metadata = {
	142	'numchannels': 8,
	143	'signals': {
	144	'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'},
15167916	145	'sda': {'ch': 7, 'name': 'SDA', 'desc': 'Serial data line'},
23fb2e12 UH	146	},
23fb2e12 UH	147	}
0588ed70	148
9a67ccfd UH	149	out = []
9a67ccfd UH	150	o = ack = d = ''
0588ed70	151	bitcount = data = 0
9a67ccfd	152	wr = startsample = -1
33e72c54 UH	153	IDLE, START, ADDRESS, DATA = range(4)
33e72c54 UH	154	state = IDLE
0588ed70	155
23fb2e12 UH	156	# Get the channel/probe number of the SCL/SDA signals.
	157	scl_bit = metadata['signals']['scl']['ch']
	158	sda_bit = metadata['signals']['sda']['ch']
0588ed70 UH	159
0588ed70 UH	160	# Get SCL/SDA bit values (0/1 for low/high) of the first sample.
a156f09e	161	s = inbuf[0]
930bd9d9 UH	162	oldscl = (s & (1 << scl_bit)) >> scl_bit
930bd9d9 UH	163	oldsda = (s & (1 << sda_bit)) >> sda_bit
0588ed70 UH	164
	165	# Loop over all samples.
	166	# TODO: Handle LAs with more/less than 8 channels.
	167	for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
0588ed70	168	# Get SCL/SDA bit values (0/1 for low/high).
930bd9d9 UH	169	scl = (s & (1 << scl_bit)) >> scl_bit
930bd9d9 UH	170	sda = (s & (1 << sda_bit)) >> sda_bit
0588ed70 UH	171
	172	# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
	173
	174	# START condition (S): SDA = falling, SCL = high
	175	if (oldsda == 1 and sda == 0) and scl == 1:
9a67ccfd UH	176	o = {'type': 'S', 'range': (samplenum, samplenum),
	177	'data': None, 'ann': None},
	178	out.append(o)
33e72c54	179	state = ADDRESS
0588ed70 UH	180	bitcount = data = 0
	181
	182	# Data latching by transmitter: SCL = low
	183	elif (scl == 0):
	184	pass # TODO
	185
	186	# Data sampling of receiver: SCL = rising
	187	elif (oldscl == 0 and scl == 1):
9a67ccfd UH	188	if startsample == -1:
9a67ccfd UH	189	startsample = samplenum
0588ed70 UH	190	bitcount += 1
0588ed70 UH	191
9a67ccfd UH	192	# out.append("%d\t\tRECEIVED BIT %d: %d\n" % \
9a67ccfd UH	193	# (samplenum, 8 - bitcount, sda))
0588ed70 UH	194
	195	# Address and data are transmitted MSB-first.
	196	data <<= 1
	197	data \|= sda
	198
	199	if bitcount != 9:
	200	continue
	201
	202	# We received 8 address/data bits and the ACK/NACK bit.
	203	data >>= 1 # Shift out unwanted ACK/NACK bit here.
9a67ccfd	204	ack = (sda == 1) and 'N' or 'A'
33e72c54	205	d = (state == ADDRESS) and (data & 0xfe) or data
33e72c54	206	if state == ADDRESS:
9a67ccfd	207	wr = (data & 1) and 1 or 0
33e72c54	208	state = DATA
9a67ccfd UH	209	o = {'type': state,
	210	'range': (startsample, samplenum - 1),
	211	'data': d, 'ann': None}
	212	if state == ADDRESS and wr == 1:
	213	o['type'] = 'AW'
	214	elif state == ADDRESS and wr == 0:
	215	o['type'] = 'AR'
	216	elif state == DATA and wr == 1:
	217	o['type'] = 'DW'
	218	elif state == DATA and wr == 0:
	219	o['type'] = 'DR'
	220	out.append(o)
	221	o = {'type': ack, 'range': (samplenum, samplenum),
	222	'data': None, 'ann': None}
	223	out.append(o)
	224	bitcount = data = startsample = 0
	225	startsample = -1
0588ed70 UH	226
	227	# STOP condition (P): SDA = rising, SCL = high
	228	elif (oldsda == 0 and sda == 1) and scl == 1:
9a67ccfd UH	229	o = {'type': 'P', 'range': (samplenum, samplenum),
	230	'data': None, 'ann': None},
	231	out.append(o)
33e72c54	232	state = IDLE
9a67ccfd	233	wr = -1
0588ed70 UH	234
	235	# Save current SDA/SCL values for the next round.
	236	oldscl = scl
	237	oldsda = sda
	238
9a67ccfd UH	239	# FIXME: Just for testing...
9a67ccfd UH	240	return str(out)
0588ed70	241
922763ab KS	242	register = {
	243	'id': 'i2c',
	244	'name': 'I2C',
	245	'longname': 'Inter-Integrated Circuit (I2C) bus',
	246	'desc': 'I2C is a two-wire, multi-master, serial bus.',
	247	'longdesc': '...',
	248	'author': 'Uwe Hermann',
	249	'email': 'uwe@hermann-uwe.de',
	250	'license': 'gplv2+',
	251	'in': ['logic'],
	252	'out': ['i2c'],
	253	'probes': [
	254	['scl', 'Serial clock line'],
	255	['sda', 'Serial data line'],
	256	],
	257	'options': {
	258	'address-space': ['Address space (in bits)', 7],
	259	},
	260	# 'start': start,
	261	# 'report': report,
	262	}
0588ed70	263
887d6cfa UH	264	# Use psyco (if available) as it results in huge performance improvements.
	265	try:
	266	import psyco
5c55017c	267	psyco.bind(decode)
887d6cfa UH	268	except ImportError:
	269	pass
	270