[libsigrokdecode.git] / decoders / enc28j60 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
##
## Permission is hereby granted, free of charge, to any person obtaining a copy
## of this software and associated documentation files (the "Software"), to deal
## in the Software without restriction, including without limitation the rights
## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
## copies of the Software, and to permit persons to whom the Software is
## furnished to do so, subject to the following conditions:
##
## The above copyright notice and this permission notice shall be included in all
## copies or substantial portions of the Software.
##
## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
## SOFTWARE.

import sigrokdecode as srd
from .lists import *

OPCODE_MASK = 0b11100000
REG_ADDR_MASK = 0b00011111

OPCODE_HANDLERS = {
    0b00000000: '_process_rcr',
    0b00100000: '_process_rbm',
    0b01000000: '_process_wcr',
    0b01100000: '_process_wbm',
    0b10000000: '_process_bfs',
    0b10100000: '_process_bfc',
    0b11100000: '_process_src',
}

(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA,
ANN_REG_ADDR, ANN_WARNING) = range(10)

REG_ADDR_ECON1 = 0x1F
BIT_ECON1_BSEL0 = 0b00000001
BIT_ECON1_BSEL1 = 0b00000010

class Decoder(srd.Decoder):
    api_version = 3
    id = 'enc28j60'
    name = 'ENC28J60'
    longname = 'Microchip ENC28J60'
    desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
    license = 'mit'
    inputs = ['spi']
    outputs = []
    tags = ['Embedded/industrial', 'Networking']
    annotations = (
        ('rcr', 'Read Control Register'),
        ('rbm', 'Read Buffer Memory'),
        ('wcr', 'Write Control Register'),
        ('wbm', 'Write Buffer Memory'),
        ('bfs', 'Bit Field Set'),
        ('bfc', 'Bit Field Clear'),
        ('src', 'System Reset Command'),
        ('data', 'Data'),
        ('reg-addr', 'Register Address'),
        ('warning', 'Warning'),
    )
    annotation_rows = (
        ('commands', 'Commands',
            (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
        ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
        ('warnings', 'Warnings', (ANN_WARNING,)),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.mosi = []
        self.miso = []
        self.ranges = []
        self.cmd_ss = None
        self.cmd_es = None
        self.range_ss = None
        self.range_es = None
        self.active = False
        self.bsel0 = None
        self.bsel1 = None

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putc(self, data):
        self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)

    def putr(self, data):
        self.put(self.range_ss, self.range_es, self.out_ann, data)

    def _process_command(self):
        if len(self.mosi) == 0:
            self.active = False
            return

        header = self.mosi[0]
        opcode = header & OPCODE_MASK

        if opcode not in OPCODE_HANDLERS:
            self._put_command_warning("Unknown opcode.")
            self.active = False
            return

        getattr(self, OPCODE_HANDLERS[opcode])()

        self.active = False

    def _get_register_name(self, reg_addr):
        if (self.bsel0 is None) or (self.bsel1 is None):
            # We don't know the bank we're in yet.
            return None
        else:
            bank = (self.bsel1 << 1) + self.bsel0
            return REGS[bank][reg_addr]

    def _put_register_header(self):
        reg_addr = self.mosi[0] & REG_ADDR_MASK
        reg_name = self._get_register_name(reg_addr)

        self.range_ss, self.range_es = self.cmd_ss, self.ranges[1][0]

        if reg_name is None:
            # We don't know the bank we're in yet.
            self.putr([ANN_REG_ADDR, [
                'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
                '?:{0:02X}'.format(reg_addr)]])
            self.putr([ANN_WARNING, ['Warning: Register bank not known yet.',
                                     'Warning']])
        else:
            self.putr([ANN_REG_ADDR, ['Reg {0}'.format(reg_name),
                                      '{0}'.format(reg_name)]])

            if (reg_name == '-') or (reg_name == 'Reserved'):
                self.putr([ANN_WARNING, ['Warning: Invalid register accessed.',
                                         'Warning']])

    def _put_data_byte(self, data, byte_index, binary=False):
        self.range_ss = self.ranges[byte_index][0]
        if byte_index == len(self.mosi) - 1:
            self.range_es = self.cmd_es
        else:
            self.range_es = self.ranges[byte_index + 1][0]

        if binary:
            self.putr([ANN_DATA, ['Data 0b{0:08b}'.format(data),
                                  '{0:08b}'.format(data)]])
        else:
            self.putr([ANN_DATA, ['Data 0x{0:02X}'.format(data),
                                  '{0:02X}'.format(data)]])

    def _put_command_warning(self, reason):
        self.putc([ANN_WARNING, ['Warning: {0}'.format(reason), 'Warning']])

    def _process_rcr(self):
        self.putc([ANN_RCR, ['Read Control Register', 'RCR']])

        if (len(self.mosi) != 2) and (len(self.mosi) != 3):
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()

        reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
        if reg_name is None:
            # We can't tell if we're accessing MAC/MII registers or not
            # Let's trust the user in this case.
            pass
        else:
            if (reg_name[0] == 'M') and (len(self.mosi) != 3):
                self._put_command_warning('Attempting to read a MAC/MII '
                    + 'register without using the dummy byte.')
                return

            if (reg_name[0] != 'M') and (len(self.mosi) != 2):
                self._put_command_warning('Attempting to read a non-MAC/MII '
                                          + 'register using the dummy byte.')
                return

        if len(self.mosi) == 2:
            self._put_data_byte(self.miso[1], 1)
        else:
            self.range_ss, self.range_es = self.ranges[1][0], self.ranges[2][0]
            self.putr([ANN_DATA, ['Dummy Byte', 'Dummy']])
            self._put_data_byte(self.miso[2], 2)

    def _process_rbm(self):
        if self.mosi[0] != 0b00111010:
            self._put_command_warning('Invalid header byte.')
            return

        self.putc([ANN_RBM, ['Read Buffer Memory: Length {0}'.format(
                             len(self.mosi) - 1), 'RBM']])

        for i in range(1, len(self.miso)):
            self._put_data_byte(self.miso[i], i)

    def _process_wcr(self):
        self.putc([ANN_WCR, ['Write Control Register', 'WCR']])

        if len(self.mosi) != 2:
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()
        self._put_data_byte(self.mosi[1], 1)

        if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
            self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
            self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1

    def _process_wbm(self):
        if self.mosi[0] != 0b01111010:
            self._put_command_warning('Invalid header byte.')
            return

        self.putc([ANN_WBM, ['Write Buffer Memory: Length {0}'.format(
                             len(self.mosi) - 1), 'WBM']])

        for i in range(1, len(self.mosi)):
            self._put_data_byte(self.mosi[i], i)

    def _process_bfc(self):
        self.putc([ANN_BFC, ['Bit Field Clear', 'BFC']])

        if len(self.mosi) != 2:
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()
        self._put_data_byte(self.mosi[1], 1, True)

        if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
            if self.mosi[1] & BIT_ECON1_BSEL0:
                self.bsel0 = 0
            if self.mosi[1] & BIT_ECON1_BSEL1:
                self.bsel1 = 0

    def _process_bfs(self):
        self.putc([ANN_BFS, ['Bit Field Set', 'BFS']])

        if len(self.mosi) != 2:
            self._put_command_warning('Invalid command length.')
            return

        self._put_register_header()
        self._put_data_byte(self.mosi[1], 1, True)

        if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
            if self.mosi[1] & BIT_ECON1_BSEL0:
                self.bsel0 = 1
            if self.mosi[1] & BIT_ECON1_BSEL1:
                self.bsel1 = 1

    def _process_src(self):
        self.putc([ANN_SRC, ['System Reset Command', 'SRC']])

        if len(self.mosi) != 1:
            self._put_command_warning('Invalid command length.')
            return

        self.bsel0 = 0
        self.bsel1 = 0

    def decode(self, ss, es, data):
        ptype, data1, data2 = data

        if ptype == 'CS-CHANGE':
            new_cs = data2

            if new_cs == 0:
                self.active = True
                self.cmd_ss = ss
                self.mosi = []
                self.miso = []
                self.ranges = []
            elif new_cs == 1:
                if self.active:
                    self.cmd_es = es
                    self._process_command()
        elif ptype == 'DATA':
            mosi, miso = data1, data2

            self.mosi.append(mosi)
            self.miso.append(miso)
            self.ranges.append((ss, es))
Commit	Line	Data
a7df1ee4 JL	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
	5	##
	6	## Permission is hereby granted, free of charge, to any person obtaining a copy
	7	## of this software and associated documentation files (the "Software"), to deal
	8	## in the Software without restriction, including without limitation the rights
	9	## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	## copies of the Software, and to permit persons to whom the Software is
	11	## furnished to do so, subject to the following conditions:
	12	##
	13	## The above copyright notice and this permission notice shall be included in all
	14	## copies or substantial portions of the Software.
	15	##
	16	## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	19	## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	22	## SOFTWARE.
	23
	24	import sigrokdecode as srd
de49d11e	25	from .lists import *
a7df1ee4 JL	26
	27	OPCODE_MASK = 0b11100000
	28	REG_ADDR_MASK = 0b00011111
	29
	30	OPCODE_HANDLERS = {
	31	0b00000000: '_process_rcr',
	32	0b00100000: '_process_rbm',
	33	0b01000000: '_process_wcr',
	34	0b01100000: '_process_wbm',
	35	0b10000000: '_process_bfs',
	36	0b10100000: '_process_bfc',
	37	0b11100000: '_process_src',
	38	}
	39
acc08e51 UH	40	(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA,
acc08e51 UH	41	ANN_REG_ADDR, ANN_WARNING) = range(10)
a7df1ee4 JL	42
	43	REG_ADDR_ECON1 = 0x1F
	44	BIT_ECON1_BSEL0 = 0b00000001
	45	BIT_ECON1_BSEL1 = 0b00000010
	46
a7df1ee4 JL	47	class Decoder(srd.Decoder):
	48	api_version = 3
	49	id = 'enc28j60'
	50	name = 'ENC28J60'
	51	longname = 'Microchip ENC28J60'
	52	desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
	53	license = 'mit'
	54	inputs = ['spi']
052be6a7	55	outputs = []
2df02753	56	tags = ['Embedded/industrial', 'Networking']
a7df1ee4 JL	57	annotations = (
	58	('rcr', 'Read Control Register'),
	59	('rbm', 'Read Buffer Memory'),
	60	('wcr', 'Write Control Register'),
	61	('wbm', 'Write Buffer Memory'),
	62	('bfs', 'Bit Field Set'),
	63	('bfc', 'Bit Field Clear'),
	64	('src', 'System Reset Command'),
	65	('data', 'Data'),
	66	('reg-addr', 'Register Address'),
	67	('warning', 'Warning'),
	68	)
	69	annotation_rows = (
	70	('commands', 'Commands',
	71	(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
	72	('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
	73	('warnings', 'Warnings', (ANN_WARNING,)),
	74	)
	75
	76	def __init__(self):
	77	self.reset()
	78
	79	def reset(self):
	80	self.mosi = []
	81	self.miso = []
	82	self.ranges = []
fbf652db UH	83	self.cmd_ss = None
fbf652db UH	84	self.cmd_es = None
3fc120d9 UH	85	self.range_ss = None
3fc120d9 UH	86	self.range_es = None
a7df1ee4 JL	87	self.active = False
	88	self.bsel0 = None
	89	self.bsel1 = None
	90
	91	def start(self):
ff73d589	92	self.out_ann = self.register(srd.OUTPUT_ANN)
a7df1ee4	93
72db471e	94	def putc(self, data):
ff73d589	95	self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)
72db471e	96
3fc120d9	97	def putr(self, data):
ff73d589	98	self.put(self.range_ss, self.range_es, self.out_ann, data)
3fc120d9	99
a7df1ee4 JL	100	def _process_command(self):
	101	if len(self.mosi) == 0:
	102	self.active = False
	103	return
	104
	105	header = self.mosi[0]
	106	opcode = header & OPCODE_MASK
	107
	108	if opcode not in OPCODE_HANDLERS:
	109	self._put_command_warning("Unknown opcode.")
	110	self.active = False
	111	return
	112
	113	getattr(self, OPCODE_HANDLERS[opcode])()
	114
	115	self.active = False
	116
	117	def _get_register_name(self, reg_addr):
	118	if (self.bsel0 is None) or (self.bsel1 is None):
	119	# We don't know the bank we're in yet.
	120	return None
	121	else:
	122	bank = (self.bsel1 << 1) + self.bsel0
	123	return REGS[bank][reg_addr]
	124
	125	def _put_register_header(self):
	126	reg_addr = self.mosi[0] & REG_ADDR_MASK
	127	reg_name = self._get_register_name(reg_addr)
	128
3fc120d9	129	self.range_ss, self.range_es = self.cmd_ss, self.ranges[1][0]
fbf652db	130
a7df1ee4 JL	131	if reg_name is None:
a7df1ee4 JL	132	# We don't know the bank we're in yet.
9306d59d UH	133	self.putr([ANN_REG_ADDR, [
	134	'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
	135	'?:{0:02X}'.format(reg_addr)]])
	136	self.putr([ANN_WARNING, ['Warning: Register bank not known yet.',
	137	'Warning']])
a7df1ee4	138	else:
9306d59d UH	139	self.putr([ANN_REG_ADDR, ['Reg {0}'.format(reg_name),
9306d59d UH	140	'{0}'.format(reg_name)]])
a7df1ee4 JL	141
a7df1ee4 JL	142	if (reg_name == '-') or (reg_name == 'Reserved'):
9306d59d UH	143	self.putr([ANN_WARNING, ['Warning: Invalid register accessed.',
9306d59d UH	144	'Warning']])
a7df1ee4 JL	145
a7df1ee4 JL	146	def _put_data_byte(self, data, byte_index, binary=False):
3fc120d9	147	self.range_ss = self.ranges[byte_index][0]
a7df1ee4	148	if byte_index == len(self.mosi) - 1:
3fc120d9	149	self.range_es = self.cmd_es
a7df1ee4	150	else:
3fc120d9	151	self.range_es = self.ranges[byte_index + 1][0]
a7df1ee4 JL	152
a7df1ee4 JL	153	if binary:
9306d59d UH	154	self.putr([ANN_DATA, ['Data 0b{0:08b}'.format(data),
9306d59d UH	155	'{0:08b}'.format(data)]])
a7df1ee4	156	else:
9306d59d UH	157	self.putr([ANN_DATA, ['Data 0x{0:02X}'.format(data),
9306d59d UH	158	'{0:02X}'.format(data)]])
a7df1ee4 JL	159
a7df1ee4 JL	160	def _put_command_warning(self, reason):
9306d59d	161	self.putc([ANN_WARNING, ['Warning: {0}'.format(reason), 'Warning']])
a7df1ee4 JL	162
a7df1ee4 JL	163	def _process_rcr(self):
72db471e	164	self.putc([ANN_RCR, ['Read Control Register', 'RCR']])
a7df1ee4 JL	165
	166	if (len(self.mosi) != 2) and (len(self.mosi) != 3):
	167	self._put_command_warning('Invalid command length.')
	168	return
	169
	170	self._put_register_header()
	171
	172	reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
	173	if reg_name is None:
	174	# We can't tell if we're accessing MAC/MII registers or not
	175	# Let's trust the user in this case.
	176	pass
	177	else:
	178	if (reg_name[0] == 'M') and (len(self.mosi) != 3):
	179	self._put_command_warning('Attempting to read a MAC/MII '
	180	+ 'register without using the dummy byte.')
	181	return
	182
	183	if (reg_name[0] != 'M') and (len(self.mosi) != 2):
	184	self._put_command_warning('Attempting to read a non-MAC/MII '
	185	+ 'register using the dummy byte.')
	186	return
	187
	188	if len(self.mosi) == 2:
	189	self._put_data_byte(self.miso[1], 1)
	190	else:
3fc120d9	191	self.range_ss, self.range_es = self.ranges[1][0], self.ranges[2][0]
9306d59d	192	self.putr([ANN_DATA, ['Dummy Byte', 'Dummy']])
a7df1ee4 JL	193	self._put_data_byte(self.miso[2], 2)
	194
	195	def _process_rbm(self):
	196	if self.mosi[0] != 0b00111010:
	197	self._put_command_warning('Invalid header byte.')
	198	return
	199
9306d59d UH	200	self.putc([ANN_RBM, ['Read Buffer Memory: Length {0}'.format(
9306d59d UH	201	len(self.mosi) - 1), 'RBM']])
a7df1ee4 JL	202
	203	for i in range(1, len(self.miso)):
	204	self._put_data_byte(self.miso[i], i)
	205
	206	def _process_wcr(self):
72db471e	207	self.putc([ANN_WCR, ['Write Control Register', 'WCR']])
a7df1ee4 JL	208
	209	if len(self.mosi) != 2:
	210	self._put_command_warning('Invalid command length.')
	211	return
	212
	213	self._put_register_header()
	214	self._put_data_byte(self.mosi[1], 1)
	215
	216	if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
	217	self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
	218	self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
	219
	220	def _process_wbm(self):
	221	if self.mosi[0] != 0b01111010:
	222	self._put_command_warning('Invalid header byte.')
	223	return
	224
9306d59d UH	225	self.putc([ANN_WBM, ['Write Buffer Memory: Length {0}'.format(
9306d59d UH	226	len(self.mosi) - 1), 'WBM']])
a7df1ee4 JL	227
	228	for i in range(1, len(self.mosi)):
	229	self._put_data_byte(self.mosi[i], i)
	230
	231	def _process_bfc(self):
72db471e	232	self.putc([ANN_BFC, ['Bit Field Clear', 'BFC']])
a7df1ee4 JL	233
	234	if len(self.mosi) != 2:
	235	self._put_command_warning('Invalid command length.')
	236	return
	237
	238	self._put_register_header()
	239	self._put_data_byte(self.mosi[1], 1, True)
	240
	241	if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
	242	if self.mosi[1] & BIT_ECON1_BSEL0:
	243	self.bsel0 = 0
	244	if self.mosi[1] & BIT_ECON1_BSEL1:
	245	self.bsel1 = 0
	246
	247	def _process_bfs(self):
72db471e	248	self.putc([ANN_BFS, ['Bit Field Set', 'BFS']])
a7df1ee4 JL	249
	250	if len(self.mosi) != 2:
	251	self._put_command_warning('Invalid command length.')
	252	return
	253
	254	self._put_register_header()
	255	self._put_data_byte(self.mosi[1], 1, True)
	256
	257	if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
	258	if self.mosi[1] & BIT_ECON1_BSEL0:
	259	self.bsel0 = 1
	260	if self.mosi[1] & BIT_ECON1_BSEL1:
	261	self.bsel1 = 1
	262
	263	def _process_src(self):
72db471e	264	self.putc([ANN_SRC, ['System Reset Command', 'SRC']])
a7df1ee4 JL	265
	266	if len(self.mosi) != 1:
	267	self._put_command_warning('Invalid command length.')
	268	return
	269
	270	self.bsel0 = 0
	271	self.bsel1 = 0
	272
	273	def decode(self, ss, es, data):
	274	ptype, data1, data2 = data
	275
	276	if ptype == 'CS-CHANGE':
	277	new_cs = data2
	278
	279	if new_cs == 0:
	280	self.active = True
fbf652db	281	self.cmd_ss = ss
a7df1ee4 JL	282	self.mosi = []
	283	self.miso = []
	284	self.ranges = []
	285	elif new_cs == 1:
	286	if self.active:
fbf652db	287	self.cmd_es = es
a7df1ee4 JL	288	self._process_command()
	289	elif ptype == 'DATA':
	290	mosi, miso = data1, data2
	291
	292	self.mosi.append(mosi)
	293	self.miso.append(miso)
	294	self.ranges.append((ss, es))