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em4100: Convert to PD API version 3
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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2015 Benjamin Larsson <benjamin@southpole.se>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
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8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
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10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
4539e9ca 17## along with this program; if not, see <http://www.gnu.org/licenses/>.
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18##
19
20import sigrokdecode as srd
21
22class SamplerateError(Exception):
23 pass
24
25class Decoder(srd.Decoder):
afb0d233 26 api_version = 3
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27 id = 'em4100'
28 name = 'EM4100'
29 longname = 'RFID EM4100'
30 desc = 'EM4100 100-150kHz RFID protocol.'
31 license = 'gplv2+'
32 inputs = ['logic']
33 outputs = ['em4100']
34 channels = (
35 {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
36 )
37 options = (
38 {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high',
39 'values': ('active-low', 'active-high')},
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40 {'id': 'datarate' , 'desc': 'Data rate', 'default': 64,
41 'values': (64, 32, 16)},
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42# {'id': 'coding', 'desc': 'Bit coding', 'default': 'biphase',
43# 'values': ('biphase', 'manchester', 'psk')},
1a782fad 44 {'id': 'coilfreq', 'desc': 'Coil frequency', 'default': 125000},
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45 )
46 annotations = (
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47 ('bit', 'Bit'),
48 ('header', 'Header'),
49 ('version-customer', 'Version/customer'),
50 ('data', 'Data'),
51 ('rowparity-ok', 'Row parity OK'),
52 ('rowparity-err', 'Row parity error'),
53 ('colparity-ok', 'Column parity OK'),
54 ('colparity-err', 'Column parity error'),
8f265907 55 ('stopbit', 'Stop bit'),
428e40cb 56 ('tag', 'Tag'),
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57 )
58 annotation_rows = (
59 ('bits', 'Bits', (0,)),
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60 ('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7, 8)),
61 ('tags', 'Tags', (9,)),
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62 )
63
92b7b49f 64 def __init__(self):
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65 self.samplerate = None
66 self.oldpin = None
67 self.last_samplenum = None
68 self.lastlast_samplenum = None
69 self.last_edge = 0
70 self.bit_width = 0
71 self.halfbit_limit = 0
72 self.oldpp = 0
73 self.oldpl = 0
74 self.oldsamplenum = 0
75 self.last_bit_pos = 0
5b0b88ce 76 self.ss_first = 0
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77 self.first_one = 0
78 self.state = 'HEADER'
79 self.data = 0
80 self.data_bits = 0
5b0b88ce 81 self.ss_data = 0
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82 self.data_parity = 0
83 self.payload_cnt = 0
84 self.data_col_parity = [0, 0, 0, 0, 0, 0]
85 self.col_parity = [0, 0, 0, 0, 0, 0]
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86 self.tag = 0
87 self.all_row_parity_ok = True
88 self.col_parity_pos = []
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89
90 def metadata(self, key, value):
91 if key == srd.SRD_CONF_SAMPLERATE:
92 self.samplerate = value
1a782fad 93 self.bit_width = (self.samplerate / self.options['coilfreq']) * self.options['datarate']
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94 self.halfbit_limit = self.bit_width/2 + self.bit_width/4
95 self.polarity = 0 if self.options['polarity'] == 'active-low' else 1
96
97 def start(self):
98 self.out_ann = self.register(srd.OUTPUT_ANN)
99
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100 def putbit(self, bit, ss, es):
101 self.put(ss, es, self.out_ann, [0, [str(bit)]])
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102 if self.state == 'HEADER':
103 if bit == 1:
104 if self.first_one > 0:
105 self.first_one += 1
106 if self.first_one == 9:
5b0b88ce 107 self.put(self.ss_first, es, self.out_ann,
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108 [1, ['Header', 'Head', 'He', 'H']])
109 self.first_one = 0
110 self.state = 'PAYLOAD'
111 return
112 if self.first_one == 0:
113 self.first_one = 1
5b0b88ce 114 self.ss_first = ss
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115
116 if bit == 0:
117 self.first_one = 0
118 return
119
120 if self.state == 'PAYLOAD':
121 self.payload_cnt += 1
122 if self.data_bits == 0:
5b0b88ce 123 self.ss_data = ss
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124 self.data = 0
125 self.data_parity = 0
126 self.data_bits += 1
127 if self.data_bits == 5:
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128 s = 'Version/customer' if self.payload_cnt <= 10 else 'Data'
129 c = 2 if self.payload_cnt <= 10 else 3
5b0b88ce 130 self.put(self.ss_data, ss, self.out_ann,
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131 [c, [s + ': %X' % self.data, '%X' % self.data]])
132 s = 'OK' if self.data_parity == bit else 'ERROR'
133 c = 4 if s == 'OK' else 5
134 if s == 'ERROR':
135 self.all_row_parity_ok = False
13090f24 136 self.put(ss, es, self.out_ann,
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137 [c, ['Row parity: ' + s, 'RP: ' + s, 'RP', 'R']])
138 self.tag = (self.tag << 4) | self.data
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139 self.data_bits = 0
140 if self.payload_cnt == 50:
141 self.state = 'TRAILER'
142 self.payload_cnt = 0
143
144 self.data_parity ^= bit
145 self.data_col_parity[self.data_bits] ^= bit
146 self.data = (self.data << 1) | bit
147 return
148
149 if self.state == 'TRAILER':
150 self.payload_cnt += 1
151 if self.data_bits == 0:
5b0b88ce 152 self.ss_data = ss
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153 self.data = 0
154 self.data_parity = 0
155 self.data_bits += 1
156 self.col_parity[self.data_bits] = bit
13090f24 157 self.col_parity_pos.append([ss, es])
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158
159 if self.data_bits == 5:
13090f24 160 self.put(ss, es, self.out_ann, [8, ['Stop bit', 'SB', 'S']])
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161
162 for i in range(1, 5):
163 s = 'OK' if self.data_col_parity[i] == \
164 self.col_parity[i] else 'ERROR'
165 c = 6 if s == 'OK' else 7
166 self.put(self.col_parity_pos[i - 1][0],
167 self.col_parity_pos[i - 1][1], self.out_ann,
168 [c, ['Column parity %d: %s' % (i, s),
169 'CP%d: %s' % (i, s), 'CP%d' % i, 'C']])
170
171 # Emit an annotation for valid-looking tags.
172 all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5])
173 if all_col_parity_ok and self.all_row_parity_ok:
5b0b88ce 174 self.put(self.ss_first, es, self.out_ann,
428e40cb 175 [9, ['Tag: %010X' % self.tag, 'Tag', 'T']])
8f265907 176
428e40cb 177 self.tag = 0
8f265907 178 self.data_bits = 0
428e40cb 179
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180 if self.payload_cnt == 5:
181 self.state = 'HEADER'
182 self.payload_cnt = 0
183 self.data_col_parity = [0, 0, 0, 0, 0, 0]
184 self.col_parity = [0, 0, 0, 0, 0, 0]
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185 self.col_parity_pos = []
186 self.all_row_parity_ok = True
8f265907 187
afb0d233 188 def manchester_decode(self, pl, pp, pin):
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189 bit = self.oldpin ^ self.polarity
190 if pl > self.halfbit_limit:
afb0d233 191 es = int(self.samplenum - pl/2)
8f265907 192 if self.oldpl > self.halfbit_limit:
13090f24 193 ss = int(self.oldsamplenum - self.oldpl/2)
91ae892d 194 else:
13090f24 195 ss = int(self.oldsamplenum - self.oldpl)
91ae892d 196 self.putbit(bit, ss, es)
afb0d233 197 self.last_bit_pos = int(self.samplenum - pl/2)
91ae892d 198 else:
afb0d233 199 es = int(self.samplenum)
8f265907 200 if self.oldpl > self.halfbit_limit:
13090f24 201 ss = int(self.oldsamplenum - self.oldpl/2)
13090f24 202 self.putbit(bit, ss, es)
afb0d233 203 self.last_bit_pos = int(self.samplenum)
91ae892d 204 else:
8f265907 205 if self.last_bit_pos <= self.oldsamplenum - self.oldpl:
13090f24 206 ss = int(self.oldsamplenum - self.oldpl)
13090f24 207 self.putbit(bit, ss, es)
afb0d233 208 self.last_bit_pos = int(self.samplenum)
8f265907 209
afb0d233 210 def decode(self):
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211 if not self.samplerate:
212 raise SamplerateError('Cannot decode without samplerate.')
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213
214 # Initialize internal state from the very first sample.
215 (pin,) = self.wait({'skip': 1})
216 self.oldpin = pin
217 self.last_samplenum = self.samplenum
218 self.lastlast_samplenum = self.samplenum
219 self.last_edge = self.samplenum
220 self.oldpl = 0
221 self.oldpp = 0
222 self.oldsamplenum = 0
223 self.last_bit_pos = 0
224
225 while True:
226 # Ignore identical samples, only process edges.
227 (pin,) = self.wait({0: 'e'})
228 pl = self.samplenum - self.oldsamplenum
229 pp = pin
230 self.manchester_decode(pl, pp, pin)
231 self.oldpl = pl
232 self.oldpp = pp
233 self.oldsamplenum = self.samplenum
234 self.oldpin = pin