[libsigrokdecode.git] / decoders / em4100 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2015 Benjamin Larsson <benjamin@southpole.se>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 3
    id = 'em4100'
    name = 'EM4100'
    longname = 'RFID EM4100'
    desc = 'EM4100 100-150kHz RFID protocol.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['em4100']
    channels = (
        {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
    )
    options = (
        {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high',
            'values': ('active-low', 'active-high')},
        {'id': 'datarate' , 'desc': 'Data rate', 'default': 64,
            'values': (64, 32, 16)},
#        {'id': 'coding', 'desc': 'Bit coding', 'default': 'biphase',
#            'values': ('biphase', 'manchester', 'psk')},
        {'id': 'coilfreq', 'desc': 'Coil frequency', 'default': 125000},
    )
    annotations = (
        ('bit', 'Bit'),
        ('header', 'Header'),
        ('version-customer', 'Version/customer'),
        ('data', 'Data'),
        ('rowparity-ok', 'Row parity OK'),
        ('rowparity-err', 'Row parity error'),
        ('colparity-ok', 'Column parity OK'),
        ('colparity-err', 'Column parity error'),
        ('stopbit', 'Stop bit'),
        ('tag', 'Tag'),
    )
    annotation_rows = (
        ('bits', 'Bits', (0,)),
        ('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7, 8)),
        ('tags', 'Tags', (9,)),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.samplerate = None
        self.oldpin = None
        self.last_samplenum = None
        self.lastlast_samplenum = None
        self.last_edge = 0
        self.bit_width = 0
        self.halfbit_limit = 0
        self.oldpp = 0
        self.oldpl = 0
        self.oldsamplenum = 0
        self.last_bit_pos = 0
        self.ss_first = 0
        self.first_one = 0
        self.state = 'HEADER'
        self.data = 0
        self.data_bits = 0
        self.ss_data = 0
        self.data_parity = 0
        self.payload_cnt = 0
        self.data_col_parity = [0, 0, 0, 0, 0, 0]
        self.col_parity = [0, 0, 0, 0, 0, 0]
        self.tag = 0
        self.all_row_parity_ok = True
        self.col_parity_pos = []

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value
        self.bit_width = (self.samplerate / self.options['coilfreq']) * self.options['datarate']
        self.halfbit_limit = self.bit_width/2 + self.bit_width/4
        self.polarity = 0 if self.options['polarity'] == 'active-low' else 1

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putbit(self, bit, ss, es):
        self.put(ss, es, self.out_ann, [0, [str(bit)]])
        if self.state == 'HEADER':
            if bit == 1:
                if self.first_one > 0:
                    self.first_one += 1
                if self.first_one == 9:
                    self.put(self.ss_first, es, self.out_ann,
                             [1, ['Header', 'Head', 'He', 'H']])
                    self.first_one = 0
                    self.state = 'PAYLOAD'
                    return
                if self.first_one == 0:
                    self.first_one = 1
                    self.ss_first = ss

            if bit == 0:
                self.first_one = 0
            return

        if self.state == 'PAYLOAD':
            self.payload_cnt += 1
            if self.data_bits == 0:
                self.ss_data = ss
                self.data = 0
                self.data_parity = 0
            self.data_bits += 1
            if self.data_bits == 5:
                s = 'Version/customer' if self.payload_cnt <= 10 else 'Data'
                c = 2 if self.payload_cnt <= 10 else 3
                self.put(self.ss_data, ss, self.out_ann,
                         [c, [s + ': %X' % self.data, '%X' % self.data]])
                s = 'OK' if self.data_parity == bit else 'ERROR'
                c = 4 if s == 'OK' else 5
                if s == 'ERROR':
                    self.all_row_parity_ok = False
                self.put(ss, es, self.out_ann,
                         [c, ['Row parity: ' + s, 'RP: ' + s, 'RP', 'R']])
                self.tag = (self.tag << 4) | self.data
                self.data_bits = 0
                if self.payload_cnt == 50:
                    self.state = 'TRAILER'
                    self.payload_cnt = 0

            self.data_parity ^= bit
            self.data_col_parity[self.data_bits] ^= bit
            self.data = (self.data << 1) | bit
            return

        if self.state == 'TRAILER':
            self.payload_cnt += 1
            if self.data_bits == 0:
                self.ss_data = ss
                self.data = 0
                self.data_parity = 0
            self.data_bits += 1
            self.col_parity[self.data_bits] = bit
            self.col_parity_pos.append([ss, es])

            if self.data_bits == 5:
                self.put(ss, es, self.out_ann, [8, ['Stop bit', 'SB', 'S']])

                for i in range(1, 5):
                    s = 'OK' if self.data_col_parity[i] == \
                                self.col_parity[i] else 'ERROR'
                    c = 6 if s == 'OK' else 7
                    self.put(self.col_parity_pos[i - 1][0],
                             self.col_parity_pos[i - 1][1], self.out_ann,
                             [c, ['Column parity %d: %s' % (i, s),
                                  'CP%d: %s' % (i, s), 'CP%d' % i, 'C']])

                # Emit an annotation for valid-looking tags.
                all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5])
                if all_col_parity_ok and self.all_row_parity_ok:
                    self.put(self.ss_first, es, self.out_ann,
                             [9, ['Tag: %010X' % self.tag, 'Tag', 'T']])

                self.tag = 0
                self.data_bits = 0

                if self.payload_cnt == 5:
                    self.state = 'HEADER'
                    self.payload_cnt = 0
                    self.data_col_parity = [0, 0, 0, 0, 0, 0]
                    self.col_parity = [0, 0, 0, 0, 0, 0]
                    self.col_parity_pos = []
                    self.all_row_parity_ok = True

    def manchester_decode(self, pl, pp, pin):
        bit = self.oldpin ^ self.polarity
        if pl > self.halfbit_limit:
            es = int(self.samplenum - pl/2)
            if self.oldpl > self.halfbit_limit:
                ss = int(self.oldsamplenum - self.oldpl/2)
            else:
                ss = int(self.oldsamplenum - self.oldpl)
            self.putbit(bit, ss, es)
            self.last_bit_pos = int(self.samplenum - pl/2)
        else:
            es = int(self.samplenum)
            if self.oldpl > self.halfbit_limit:
                ss = int(self.oldsamplenum - self.oldpl/2)
                self.putbit(bit, ss, es)
                self.last_bit_pos = int(self.samplenum)
            else:
                if self.last_bit_pos <= self.oldsamplenum - self.oldpl:
                    ss = int(self.oldsamplenum - self.oldpl)
                    self.putbit(bit, ss, es)
                    self.last_bit_pos = int(self.samplenum)

    def decode(self):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')

        # Initialize internal state from the very first sample.
        (pin,) = self.wait()
        self.oldpin = pin
        self.last_samplenum = self.samplenum
        self.lastlast_samplenum = self.samplenum
        self.last_edge = self.samplenum
        self.oldpl = 0
        self.oldpp = 0
        self.oldsamplenum = 0
        self.last_bit_pos = 0

        while True:
            # Ignore identical samples, only process edges.
            (pin,) = self.wait({0: 'e'})
            pl = self.samplenum - self.oldsamplenum
            pp = pin
            self.manchester_decode(pl, pp, pin)
            self.oldpl = pl
            self.oldpp = pp
            self.oldsamplenum = self.samplenum
            self.oldpin = pin
Commit	Line	Data
8f265907 BL	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2015 Benjamin Larsson <benjamin@southpole.se>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
88df2c9a UH	8	## the Free Software Foundation; either version 2 of the License, or
88df2c9a UH	9	## (at your option) any later version.
8f265907 BL	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
4539e9ca	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
8f265907 BL	18	##
	19
	20	import sigrokdecode as srd
	21
	22	class SamplerateError(Exception):
	23	pass
	24
	25	class Decoder(srd.Decoder):
afb0d233	26	api_version = 3
8f265907 BL	27	id = 'em4100'
	28	name = 'EM4100'
	29	longname = 'RFID EM4100'
	30	desc = 'EM4100 100-150kHz RFID protocol.'
	31	license = 'gplv2+'
	32	inputs = ['logic']
	33	outputs = ['em4100']
	34	channels = (
	35	{'id': 'data', 'name': 'Data', 'desc': 'Data line'},
	36	)
	37	options = (
	38	{'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high',
	39	'values': ('active-low', 'active-high')},
1a782fad UH	40	{'id': 'datarate' , 'desc': 'Data rate', 'default': 64,
1a782fad UH	41	'values': (64, 32, 16)},
8f265907 BL	42	# {'id': 'coding', 'desc': 'Bit coding', 'default': 'biphase',
8f265907 BL	43	# 'values': ('biphase', 'manchester', 'psk')},
1a782fad	44	{'id': 'coilfreq', 'desc': 'Coil frequency', 'default': 125000},
8f265907 BL	45	)
8f265907 BL	46	annotations = (
428e40cb UH	47	('bit', 'Bit'),
	48	('header', 'Header'),
	49	('version-customer', 'Version/customer'),
	50	('data', 'Data'),
	51	('rowparity-ok', 'Row parity OK'),
	52	('rowparity-err', 'Row parity error'),
	53	('colparity-ok', 'Column parity OK'),
	54	('colparity-err', 'Column parity error'),
8f265907	55	('stopbit', 'Stop bit'),
428e40cb	56	('tag', 'Tag'),
8f265907 BL	57	)
	58	annotation_rows = (
	59	('bits', 'Bits', (0,)),
428e40cb UH	60	('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7, 8)),
428e40cb UH	61	('tags', 'Tags', (9,)),
8f265907 BL	62	)
8f265907 BL	63
92b7b49f	64	def __init__(self):
10aeb8ea GS	65	self.reset()
	66
	67	def reset(self):
8f265907 BL	68	self.samplerate = None
	69	self.oldpin = None
	70	self.last_samplenum = None
	71	self.lastlast_samplenum = None
	72	self.last_edge = 0
	73	self.bit_width = 0
	74	self.halfbit_limit = 0
	75	self.oldpp = 0
	76	self.oldpl = 0
	77	self.oldsamplenum = 0
	78	self.last_bit_pos = 0
5b0b88ce	79	self.ss_first = 0
8f265907 BL	80	self.first_one = 0
	81	self.state = 'HEADER'
	82	self.data = 0
	83	self.data_bits = 0
5b0b88ce	84	self.ss_data = 0
8f265907 BL	85	self.data_parity = 0
	86	self.payload_cnt = 0
	87	self.data_col_parity = [0, 0, 0, 0, 0, 0]
	88	self.col_parity = [0, 0, 0, 0, 0, 0]
428e40cb UH	89	self.tag = 0
	90	self.all_row_parity_ok = True
	91	self.col_parity_pos = []
8f265907 BL	92
	93	def metadata(self, key, value):
	94	if key == srd.SRD_CONF_SAMPLERATE:
	95	self.samplerate = value
1a782fad	96	self.bit_width = (self.samplerate / self.options['coilfreq']) * self.options['datarate']
8f265907 BL	97	self.halfbit_limit = self.bit_width/2 + self.bit_width/4
	98	self.polarity = 0 if self.options['polarity'] == 'active-low' else 1
	99
	100	def start(self):
	101	self.out_ann = self.register(srd.OUTPUT_ANN)
	102
91ae892d UH	103	def putbit(self, bit, ss, es):
91ae892d UH	104	self.put(ss, es, self.out_ann, [0, [str(bit)]])
8f265907 BL	105	if self.state == 'HEADER':
	106	if bit == 1:
	107	if self.first_one > 0:
	108	self.first_one += 1
	109	if self.first_one == 9:
5b0b88ce	110	self.put(self.ss_first, es, self.out_ann,
8f265907 BL	111	[1, ['Header', 'Head', 'He', 'H']])
	112	self.first_one = 0
	113	self.state = 'PAYLOAD'
	114	return
	115	if self.first_one == 0:
	116	self.first_one = 1
5b0b88ce	117	self.ss_first = ss
8f265907 BL	118
	119	if bit == 0:
	120	self.first_one = 0
	121	return
	122
	123	if self.state == 'PAYLOAD':
	124	self.payload_cnt += 1
	125	if self.data_bits == 0:
5b0b88ce	126	self.ss_data = ss
8f265907 BL	127	self.data = 0
	128	self.data_parity = 0
	129	self.data_bits += 1
	130	if self.data_bits == 5:
428e40cb UH	131	s = 'Version/customer' if self.payload_cnt <= 10 else 'Data'
428e40cb UH	132	c = 2 if self.payload_cnt <= 10 else 3
5b0b88ce	133	self.put(self.ss_data, ss, self.out_ann,
428e40cb UH	134	[c, [s + ': %X' % self.data, '%X' % self.data]])
	135	s = 'OK' if self.data_parity == bit else 'ERROR'
	136	c = 4 if s == 'OK' else 5
	137	if s == 'ERROR':
	138	self.all_row_parity_ok = False
13090f24	139	self.put(ss, es, self.out_ann,
428e40cb UH	140	[c, ['Row parity: ' + s, 'RP: ' + s, 'RP', 'R']])
428e40cb UH	141	self.tag = (self.tag << 4) \| self.data
8f265907 BL	142	self.data_bits = 0
	143	if self.payload_cnt == 50:
	144	self.state = 'TRAILER'
	145	self.payload_cnt = 0
	146
	147	self.data_parity ^= bit
	148	self.data_col_parity[self.data_bits] ^= bit
	149	self.data = (self.data << 1) \| bit
	150	return
	151
	152	if self.state == 'TRAILER':
	153	self.payload_cnt += 1
	154	if self.data_bits == 0:
5b0b88ce	155	self.ss_data = ss
8f265907 BL	156	self.data = 0
	157	self.data_parity = 0
	158	self.data_bits += 1
	159	self.col_parity[self.data_bits] = bit
13090f24	160	self.col_parity_pos.append([ss, es])
8f265907 BL	161
8f265907 BL	162	if self.data_bits == 5:
13090f24	163	self.put(ss, es, self.out_ann, [8, ['Stop bit', 'SB', 'S']])
428e40cb UH	164
	165	for i in range(1, 5):
	166	s = 'OK' if self.data_col_parity[i] == \
	167	self.col_parity[i] else 'ERROR'
	168	c = 6 if s == 'OK' else 7
	169	self.put(self.col_parity_pos[i - 1][0],
	170	self.col_parity_pos[i - 1][1], self.out_ann,
	171	[c, ['Column parity %d: %s' % (i, s),
	172	'CP%d: %s' % (i, s), 'CP%d' % i, 'C']])
	173
	174	# Emit an annotation for valid-looking tags.
	175	all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5])
	176	if all_col_parity_ok and self.all_row_parity_ok:
5b0b88ce	177	self.put(self.ss_first, es, self.out_ann,
428e40cb	178	[9, ['Tag: %010X' % self.tag, 'Tag', 'T']])
8f265907	179
428e40cb	180	self.tag = 0
8f265907	181	self.data_bits = 0
428e40cb	182
8f265907 BL	183	if self.payload_cnt == 5:
	184	self.state = 'HEADER'
	185	self.payload_cnt = 0
	186	self.data_col_parity = [0, 0, 0, 0, 0, 0]
	187	self.col_parity = [0, 0, 0, 0, 0, 0]
428e40cb UH	188	self.col_parity_pos = []
428e40cb UH	189	self.all_row_parity_ok = True
8f265907	190
afb0d233	191	def manchester_decode(self, pl, pp, pin):
8f265907 BL	192	bit = self.oldpin ^ self.polarity
8f265907 BL	193	if pl > self.halfbit_limit:
afb0d233	194	es = int(self.samplenum - pl/2)
8f265907	195	if self.oldpl > self.halfbit_limit:
13090f24	196	ss = int(self.oldsamplenum - self.oldpl/2)
91ae892d	197	else:
13090f24	198	ss = int(self.oldsamplenum - self.oldpl)
91ae892d	199	self.putbit(bit, ss, es)
afb0d233	200	self.last_bit_pos = int(self.samplenum - pl/2)
91ae892d	201	else:
afb0d233	202	es = int(self.samplenum)
8f265907	203	if self.oldpl > self.halfbit_limit:
13090f24	204	ss = int(self.oldsamplenum - self.oldpl/2)
13090f24	205	self.putbit(bit, ss, es)
afb0d233	206	self.last_bit_pos = int(self.samplenum)
91ae892d	207	else:
8f265907	208	if self.last_bit_pos <= self.oldsamplenum - self.oldpl:
13090f24	209	ss = int(self.oldsamplenum - self.oldpl)
13090f24	210	self.putbit(bit, ss, es)
afb0d233	211	self.last_bit_pos = int(self.samplenum)
8f265907	212
afb0d233	213	def decode(self):
8f265907 BL	214	if not self.samplerate:
8f265907 BL	215	raise SamplerateError('Cannot decode without samplerate.')
afb0d233 GS	216
afb0d233 GS	217	# Initialize internal state from the very first sample.
1b9ef18b	218	(pin,) = self.wait()
afb0d233 GS	219	self.oldpin = pin
	220	self.last_samplenum = self.samplenum
	221	self.lastlast_samplenum = self.samplenum
	222	self.last_edge = self.samplenum
	223	self.oldpl = 0
	224	self.oldpp = 0
	225	self.oldsamplenum = 0
	226	self.last_bit_pos = 0
	227
	228	while True:
	229	# Ignore identical samples, only process edges.
	230	(pin,) = self.wait({0: 'e'})
	231	pl = self.samplenum - self.oldsamplenum
	232	pp = pin
	233	self.manchester_decode(pl, pp, pin)
	234	self.oldpl = pl
	235	self.oldpp = pp
	236	self.oldsamplenum = self.samplenum
	237	self.oldpin = pin