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702fa251 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
702fa251 | 3 | ## |
e20f455c | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
38b40330 | 5 | ## Copyright (C) 2019 Stephan Thiele <stephan.thiele@mailbox.org> |
702fa251 UH |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 18 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
702fa251 | 19 | ## |
702fa251 UH |
20 | |
21 | import sigrokdecode as srd | |
22 | ||
21cda951 UH |
23 | class SamplerateError(Exception): |
24 | pass | |
25 | ||
702fa251 | 26 | class Decoder(srd.Decoder): |
64d87119 | 27 | api_version = 3 |
702fa251 UH |
28 | id = 'can' |
29 | name = 'CAN' | |
9e1437a0 | 30 | longname = 'Controller Area Network' |
702fa251 UH |
31 | desc = 'Field bus protocol for distributed realtime control.' |
32 | license = 'gplv2+' | |
33 | inputs = ['logic'] | |
6cbba91f | 34 | outputs = [] |
d6d8a8a4 | 35 | tags = ['Automotive'] |
6a15597a | 36 | channels = ( |
702fa251 | 37 | {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, |
da9bcbd9 | 38 | ) |
84c1c0b5 | 39 | options = ( |
b0918d40 UH |
40 | {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000}, |
41 | {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, | |
84c1c0b5 | 42 | ) |
da9bcbd9 BV |
43 | annotations = ( |
44 | ('data', 'CAN payload data'), | |
45 | ('sof', 'Start of frame'), | |
46 | ('eof', 'End of frame'), | |
47 | ('id', 'Identifier'), | |
48 | ('ext-id', 'Extended identifier'), | |
49 | ('full-id', 'Full identifier'), | |
50 | ('ide', 'Identifier extension bit'), | |
51 | ('reserved-bit', 'Reserved bit 0 and 1'), | |
52 | ('rtr', 'Remote transmission request'), | |
53 | ('srr', 'Substitute remote request'), | |
54 | ('dlc', 'Data length count'), | |
55 | ('crc-sequence', 'CRC sequence'), | |
56 | ('crc-delimiter', 'CRC delimiter'), | |
57 | ('ack-slot', 'ACK slot'), | |
58 | ('ack-delimiter', 'ACK delimiter'), | |
59 | ('stuff-bit', 'Stuff bit'), | |
60 | ('warnings', 'Human-readable warnings'), | |
544038d9 | 61 | ('bit', 'Bit'), |
d4a28d0f UH |
62 | ) |
63 | annotation_rows = ( | |
544038d9 | 64 | ('bits', 'Bits', (15, 17)), |
2fac4493 UH |
65 | ('fields', 'Fields', tuple(range(15))), |
66 | ('warnings', 'Warnings', (16,)), | |
da9bcbd9 | 67 | ) |
702fa251 | 68 | |
92b7b49f | 69 | def __init__(self): |
10aeb8ea GS |
70 | self.reset() |
71 | ||
0102e92b ST |
72 | def dlc2len(self, dlc): |
73 | return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc] | |
74 | ||
10aeb8ea | 75 | def reset(self): |
f372d597 | 76 | self.samplerate = None |
702fa251 UH |
77 | self.reset_variables() |
78 | ||
f372d597 | 79 | def start(self): |
be465111 | 80 | self.out_ann = self.register(srd.OUTPUT_ANN) |
702fa251 | 81 | |
f372d597 BV |
82 | def metadata(self, key, value): |
83 | if key == srd.SRD_CONF_SAMPLERATE: | |
84 | self.samplerate = value | |
85 | self.bit_width = float(self.samplerate) / float(self.options['bitrate']) | |
300f9194 | 86 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] |
702fa251 | 87 | |
4b1813b4 UH |
88 | # Generic helper for CAN bit annotations. |
89 | def putg(self, ss, es, data): | |
300f9194 | 90 | left, right = int(self.sample_point), int(self.bit_width - self.sample_point) |
4b1813b4 UH |
91 | self.put(ss - left, es + right, self.out_ann, data) |
92 | ||
93 | # Single-CAN-bit annotation using the current samplenum. | |
e20f455c | 94 | def putx(self, data): |
4b1813b4 UH |
95 | self.putg(self.samplenum, self.samplenum, data) |
96 | ||
97 | # Single-CAN-bit annotation using the samplenum of CAN bit 12. | |
98 | def put12(self, data): | |
99 | self.putg(self.ss_bit12, self.ss_bit12, data) | |
100 | ||
101 | # Multi-CAN-bit annotation from self.ss_block to current samplenum. | |
102 | def putb(self, data): | |
103 | self.putg(self.ss_block, self.samplenum, data) | |
e20f455c | 104 | |
702fa251 UH |
105 | def reset_variables(self): |
106 | self.state = 'IDLE' | |
107 | self.sof = self.frame_type = self.dlc = None | |
108 | self.rawbits = [] # All bits, including stuff bits | |
109 | self.bits = [] # Only actual CAN frame bits (no stuff bits) | |
110 | self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) | |
111 | self.last_databit = 999 # Positive value that bitnum+x will never match | |
4b1813b4 UH |
112 | self.ss_block = None |
113 | self.ss_bit12 = None | |
114 | self.ss_databytebits = [] | |
702fa251 | 115 | |
45a50880 GS |
116 | # Poor man's clock synchronization. Use signal edges which change to |
117 | # dominant state in rather simple ways. This naive approach is neither | |
118 | # aware of the SYNC phase's width nor the specific location of the edge, | |
119 | # but improves the decoder's reliability when the input signal's bitrate | |
120 | # does not exactly match the nominal rate. | |
121 | def dom_edge_seen(self, force = False): | |
122 | self.dom_edge_snum = self.samplenum | |
123 | self.dom_edge_bcount = self.curbit | |
124 | ||
125 | def bit_sampled(self): | |
126 | # EMPTY | |
127 | pass | |
128 | ||
64d87119 GS |
129 | # Determine the position of the next desired bit's sample point. |
130 | def get_sample_point(self, bitnum): | |
45a50880 GS |
131 | samplenum = self.dom_edge_snum |
132 | samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount)) | |
133 | samplenum += int(self.sample_point) | |
300f9194 | 134 | return samplenum |
702fa251 UH |
135 | |
136 | def is_stuff_bit(self): | |
137 | # CAN uses NRZ encoding and bit stuffing. | |
138 | # After 5 identical bits, a stuff bit of opposite value is added. | |
a0128522 | 139 | # But not in the CRC delimiter, ACK, and end of frame fields. |
cffb6592 | 140 | if len(self.bits) > self.last_databit + 17: |
a0128522 | 141 | return False |
702fa251 UH |
142 | last_6_bits = self.rawbits[-6:] |
143 | if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): | |
144 | return False | |
145 | ||
146 | # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. | |
702fa251 UH |
147 | self.bits.pop() # Drop last bit. |
148 | return True | |
149 | ||
150 | def is_valid_crc(self, crc_bits): | |
151 | return True # TODO | |
152 | ||
153 | def decode_error_frame(self, bits): | |
154 | pass # TODO | |
155 | ||
156 | def decode_overload_frame(self, bits): | |
157 | pass # TODO | |
158 | ||
159 | # Both standard and extended frames end with CRC, CRC delimiter, ACK, | |
160 | # ACK delimiter, and EOF fields. Handle them in a common function. | |
161 | # Returns True if the frame ended (EOF), False otherwise. | |
162 | def decode_frame_end(self, can_rx, bitnum): | |
163 | ||
4b1813b4 UH |
164 | # Remember start of CRC sequence (see below). |
165 | if bitnum == (self.last_databit + 1): | |
166 | self.ss_block = self.samplenum | |
167 | ||
741dba78 ST |
168 | if self.fd: |
169 | if self.dlc < 16: | |
170 | self.crc_len = 27 # 17 + SBC + stuff bits | |
171 | else: | |
172 | self.crc_len = 21 | |
173 | else: | |
174 | self.crc_len = 15 | |
175 | ||
176 | # CRC sequence (15 bits, 17 bits or 21 bits) | |
177 | elif bitnum == (self.last_databit + self.crc_len): | |
178 | if self.fd: | |
179 | if self.dlc < 16: | |
180 | crc_type = "CRC-17" | |
181 | else: | |
182 | crc_type = "CRC-21" | |
183 | else: | |
184 | crc_type = "CRC-15" | |
185 | ||
702fa251 | 186 | x = self.last_databit + 1 |
741dba78 | 187 | crc_bits = self.bits[x:x + self.crc_len + 1] |
702fa251 | 188 | self.crc = int(''.join(str(d) for d in crc_bits), 2) |
741dba78 ST |
189 | self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc), |
190 | '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]]) | |
702fa251 | 191 | if not self.is_valid_crc(crc_bits): |
74c9bb3c | 192 | self.putb([16, ['CRC is invalid']]) |
702fa251 UH |
193 | |
194 | # CRC delimiter bit (recessive) | |
741dba78 | 195 | elif bitnum == (self.last_databit + self.crc_len + 1): |
74c9bb3c UH |
196 | self.putx([12, ['CRC delimiter: %d' % can_rx, |
197 | 'CRC d: %d' % can_rx, 'CRC d']]) | |
2fac4493 UH |
198 | if can_rx != 1: |
199 | self.putx([16, ['CRC delimiter must be a recessive bit']]) | |
702fa251 UH |
200 | |
201 | # ACK slot bit (dominant: ACK, recessive: NACK) | |
741dba78 | 202 | elif bitnum == (self.last_databit + self.crc_len + 2): |
702fa251 | 203 | ack = 'ACK' if can_rx == 0 else 'NACK' |
74c9bb3c | 204 | self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) |
702fa251 UH |
205 | |
206 | # ACK delimiter bit (recessive) | |
741dba78 | 207 | elif bitnum == (self.last_databit + self.crc_len + 3): |
74c9bb3c UH |
208 | self.putx([14, ['ACK delimiter: %d' % can_rx, |
209 | 'ACK d: %d' % can_rx, 'ACK d']]) | |
2fac4493 UH |
210 | if can_rx != 1: |
211 | self.putx([16, ['ACK delimiter must be a recessive bit']]) | |
702fa251 | 212 | |
4b1813b4 | 213 | # Remember start of EOF (see below). |
741dba78 | 214 | elif bitnum == (self.last_databit + self.crc_len + 4): |
4b1813b4 UH |
215 | self.ss_block = self.samplenum |
216 | ||
702fa251 | 217 | # End of frame (EOF), 7 recessive bits |
741dba78 | 218 | elif bitnum == (self.last_databit + self.crc_len + 11): |
74c9bb3c | 219 | self.putb([2, ['End of frame', 'EOF', 'E']]) |
2fac4493 UH |
220 | if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: |
221 | self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) | |
702fa251 UH |
222 | self.reset_variables() |
223 | return True | |
224 | ||
225 | return False | |
226 | ||
227 | # Returns True if the frame ended (EOF), False otherwise. | |
228 | def decode_standard_frame(self, can_rx, bitnum): | |
229 | ||
38b40330 ST |
230 | # Bit 14: FDF (Flexible Data Format) |
231 | # Has to be sent dominant when FD frame, has to be sent recessive when classic CAN frame. | |
702fa251 | 232 | if bitnum == 14: |
38b40330 ST |
233 | self.fd = True if can_rx else False |
234 | ||
235 | self.putx([7, ['Flexible Data Format: %d' % can_rx, | |
7f75d507 ST |
236 | 'FDF: %d' % can_rx, |
237 | 'FDF']]) | |
38b40330 ST |
238 | |
239 | # SRR Substitute Remote Request | |
240 | if self.fd: | |
241 | self.put12([8, ['Substitute Remote Request', 'SRR']]) | |
7f75d507 | 242 | self.dlc_start = 18 |
38b40330 ST |
243 | else: |
244 | # Bit 12: Remote transmission request (RTR) bit | |
245 | # Data frame: dominant, remote frame: recessive | |
246 | # Remote frames do not contain a data field. | |
247 | rtr = 'remote' if self.bits[12] == 1 else 'data' | |
248 | self.put12([8, ['Remote transmission request: %s frame' % rtr, | |
249 | 'RTR: %s frame' % rtr, 'RTR']]) | |
7f75d507 | 250 | self.dlc_start = 15 |
38b40330 ST |
251 | |
252 | # TODO: add Res, BRS and ESI bits when FD format: | |
7f75d507 ST |
253 | if bitnum == 15: |
254 | if self.fd: | |
255 | self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']]) | |
256 | ||
257 | if bitnum == 16: | |
258 | if self.fd: | |
259 | self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']]) | |
702fa251 | 260 | |
7f75d507 ST |
261 | if bitnum == 17: |
262 | if self.fd: | |
263 | self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']]) | |
4b1813b4 UH |
264 | |
265 | # Remember start of DLC (see below). | |
7f75d507 | 266 | elif bitnum == self.dlc_start: |
4b1813b4 | 267 | self.ss_block = self.samplenum |
702fa251 UH |
268 | |
269 | # Bits 15-18: Data length code (DLC), in number of bytes (0-8). | |
7f75d507 ST |
270 | elif bitnum == self.dlc_start + 3: |
271 | self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2) | |
0102e92b ST |
272 | self.putb([10, ['Data length code: %d (%d Bytes)' % (self.dlc, self.dlc2len(self.dlc)), |
273 | 'DLC: %d (%d B)' % (self.dlc, self.dlc2len(self.dlc)), 'DLC']]) | |
7f75d507 | 274 | self.last_databit = self.dlc_start + 3 + (self.dlc * 8) |
2fac4493 UH |
275 | if self.dlc > 8: |
276 | self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) | |
702fa251 | 277 | |
4b1813b4 | 278 | # Remember all databyte bits, except the very last one. |
7f75d507 | 279 | elif bitnum in range(self.dlc_start + 4, self.last_databit): |
4b1813b4 UH |
280 | self.ss_databytebits.append(self.samplenum) |
281 | ||
702fa251 UH |
282 | # Bits 19-X: Data field (0-8 bytes, depending on DLC) |
283 | # The bits within a data byte are transferred MSB-first. | |
284 | elif bitnum == self.last_databit: | |
4b1813b4 | 285 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 | 286 | for i in range(self.dlc): |
7f75d507 | 287 | x = self.dlc_start + 4 + (8 * i) |
702fa251 | 288 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) |
4b1813b4 UH |
289 | ss = self.ss_databytebits[i * 8] |
290 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
291 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
292 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 293 | self.ss_databytebits = [] |
702fa251 UH |
294 | |
295 | elif bitnum > self.last_databit: | |
296 | return self.decode_frame_end(can_rx, bitnum) | |
297 | ||
298 | return False | |
299 | ||
300 | # Returns True if the frame ended (EOF), False otherwise. | |
301 | def decode_extended_frame(self, can_rx, bitnum): | |
302 | ||
4b1813b4 UH |
303 | # Remember start of EID (see below). |
304 | if bitnum == 14: | |
305 | self.ss_block = self.samplenum | |
306 | ||
702fa251 | 307 | # Bits 14-31: Extended identifier (EID[17..0]) |
4b1813b4 | 308 | elif bitnum == 31: |
702fa251 | 309 | self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) |
534ae912 | 310 | s = '%d (0x%x)' % (self.eid, self.eid) |
74c9bb3c | 311 | self.putb([4, ['Extended Identifier: %s' % s, |
534ae912 | 312 | 'Extended ID: %s' % s, 'Extended ID', 'EID']]) |
702fa251 UH |
313 | |
314 | self.fullid = self.id << 18 | self.eid | |
534ae912 | 315 | s = '%d (0x%x)' % (self.fullid, self.fullid) |
74c9bb3c | 316 | self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, |
534ae912 | 317 | 'Full ID', 'FID']]) |
702fa251 UH |
318 | |
319 | # Bit 12: Substitute remote request (SRR) bit | |
74c9bb3c | 320 | self.put12([9, ['Substitute remote request: %d' % self.bits[12], |
534ae912 | 321 | 'SRR: %d' % self.bits[12], 'SRR']]) |
702fa251 UH |
322 | |
323 | # Bit 32: Remote transmission request (RTR) bit | |
324 | # Data frame: dominant, remote frame: recessive | |
325 | # Remote frames do not contain a data field. | |
326 | if bitnum == 32: | |
327 | rtr = 'remote' if can_rx == 1 else 'data' | |
74c9bb3c | 328 | self.putx([8, ['Remote transmission request: %s frame' % rtr, |
534ae912 | 329 | 'RTR: %s frame' % rtr, 'RTR']]) |
702fa251 UH |
330 | |
331 | # Bit 33: RB1 (reserved bit) | |
332 | elif bitnum == 33: | |
74c9bb3c | 333 | self.putx([7, ['Reserved bit 1: %d' % can_rx, |
534ae912 | 334 | 'RB1: %d' % can_rx, 'RB1']]) |
702fa251 UH |
335 | |
336 | # Bit 34: RB0 (reserved bit) | |
337 | elif bitnum == 34: | |
74c9bb3c | 338 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 339 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 | 340 | |
4b1813b4 UH |
341 | # Remember start of DLC (see below). |
342 | elif bitnum == 35: | |
343 | self.ss_block = self.samplenum | |
344 | ||
702fa251 UH |
345 | # Bits 35-38: Data length code (DLC), in number of bytes (0-8). |
346 | elif bitnum == 38: | |
347 | self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) | |
74c9bb3c UH |
348 | self.putb([10, ['Data length code: %d' % self.dlc, |
349 | 'DLC: %d' % self.dlc, 'DLC']]) | |
702fa251 UH |
350 | self.last_databit = 38 + (self.dlc * 8) |
351 | ||
4b1813b4 UH |
352 | # Remember all databyte bits, except the very last one. |
353 | elif bitnum in range(39, self.last_databit): | |
354 | self.ss_databytebits.append(self.samplenum) | |
355 | ||
702fa251 UH |
356 | # Bits 39-X: Data field (0-8 bytes, depending on DLC) |
357 | # The bits within a data byte are transferred MSB-first. | |
358 | elif bitnum == self.last_databit: | |
4b1813b4 | 359 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
360 | for i in range(self.dlc): |
361 | x = 38 + (8 * i) + 1 | |
362 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
363 | ss = self.ss_databytebits[i * 8] |
364 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
365 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
366 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 367 | self.ss_databytebits = [] |
702fa251 UH |
368 | |
369 | elif bitnum > self.last_databit: | |
370 | return self.decode_frame_end(can_rx, bitnum) | |
371 | ||
372 | return False | |
373 | ||
374 | def handle_bit(self, can_rx): | |
375 | self.rawbits.append(can_rx) | |
376 | self.bits.append(can_rx) | |
377 | ||
378 | # Get the index of the current CAN frame bit (without stuff bits). | |
379 | bitnum = len(self.bits) - 1 | |
380 | ||
702fa251 UH |
381 | # If this is a stuff bit, remove it from self.bits and ignore it. |
382 | if self.is_stuff_bit(): | |
544038d9 | 383 | self.putx([15, [str(can_rx)]]) |
702fa251 UH |
384 | self.curbit += 1 # Increase self.curbit (bitnum is not affected). |
385 | return | |
544038d9 UH |
386 | else: |
387 | self.putx([17, [str(can_rx)]]) | |
702fa251 UH |
388 | |
389 | # Bit 0: Start of frame (SOF) bit | |
390 | if bitnum == 0: | |
2fac4493 UH |
391 | self.putx([1, ['Start of frame', 'SOF', 'S']]) |
392 | if can_rx != 0: | |
74c9bb3c | 393 | self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) |
702fa251 | 394 | |
4b1813b4 UH |
395 | # Remember start of ID (see below). |
396 | elif bitnum == 1: | |
397 | self.ss_block = self.samplenum | |
398 | ||
702fa251 UH |
399 | # Bits 1-11: Identifier (ID[10..0]) |
400 | # The bits ID[10..4] must NOT be all recessive. | |
401 | elif bitnum == 11: | |
402 | self.id = int(''.join(str(d) for d in self.bits[1:]), 2) | |
534ae912 | 403 | s = '%d (0x%x)' % (self.id, self.id), |
74c9bb3c | 404 | self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) |
2fac4493 UH |
405 | if (self.id & 0x7f0) == 0x7f0: |
406 | self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) | |
702fa251 UH |
407 | |
408 | # RTR or SRR bit, depending on frame type (gets handled later). | |
409 | elif bitnum == 12: | |
4b1813b4 UH |
410 | # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. |
411 | self.ss_bit12 = self.samplenum | |
702fa251 UH |
412 | |
413 | # Bit 13: Identifier extension (IDE) bit | |
414 | # Standard frame: dominant, extended frame: recessive | |
415 | elif bitnum == 13: | |
416 | ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' | |
74c9bb3c | 417 | self.putx([6, ['Identifier extension bit: %s frame' % ide, |
534ae912 | 418 | 'IDE: %s frame' % ide, 'IDE']]) |
702fa251 UH |
419 | |
420 | # Bits 14-X: Frame-type dependent, passed to the resp. handlers. | |
421 | elif bitnum >= 14: | |
422 | if self.frame_type == 'standard': | |
423 | done = self.decode_standard_frame(can_rx, bitnum) | |
424 | else: | |
425 | done = self.decode_extended_frame(can_rx, bitnum) | |
426 | ||
427 | # The handlers return True if a frame ended (EOF). | |
428 | if done: | |
429 | return | |
430 | ||
431 | # After a frame there are 3 intermission bits (recessive). | |
432 | # After these bits, the bus is considered free. | |
433 | ||
434 | self.curbit += 1 | |
435 | ||
64d87119 | 436 | def decode(self): |
21cda951 UH |
437 | if not self.samplerate: |
438 | raise SamplerateError('Cannot decode without samplerate.') | |
702fa251 | 439 | |
64d87119 | 440 | while True: |
702fa251 UH |
441 | # State machine. |
442 | if self.state == 'IDLE': | |
443 | # Wait for a dominant state (logic 0) on the bus. | |
64d87119 | 444 | (can_rx,) = self.wait({0: 'l'}) |
702fa251 | 445 | self.sof = self.samplenum |
45a50880 | 446 | self.dom_edge_seen(force = True) |
702fa251 UH |
447 | self.state = 'GET BITS' |
448 | elif self.state == 'GET BITS': | |
449 | # Wait until we're in the correct bit/sampling position. | |
64d87119 | 450 | pos = self.get_sample_point(self.curbit) |
45a50880 GS |
451 | (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) |
452 | if self.matched[1]: | |
453 | self.dom_edge_seen() | |
454 | if self.matched[0]: | |
455 | self.handle_bit(can_rx) | |
456 | self.bit_sampled() |