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all decoders: introduce a reset() method
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e96593c1 1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2016 fenugrec <fenugrec users.sourceforge.net>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
4539e9ca 17## along with this program; if not, see <http://www.gnu.org/licenses/>.
e96593c1 18##
19
20# TODO:
21# - Annotations are very crude and could be improved.
22# - Annotate every nibble? Would give insight on interrupted shifts.
23# - Annotate invalid "command" nibbles while SYNC==1?
24
25import sigrokdecode as srd
26
27class Decoder(srd.Decoder):
86e7c29c 28 api_version = 3
e96593c1 29 id = 'aud'
30 name = 'AUD'
31 longname = 'Advanced User Debugger'
32 desc = 'Renesas/Hitachi Advanced User Debugger (AUD) protocol.'
33 license = 'gplv2+'
34 inputs = ['logic']
35 outputs = ['aud']
36 channels = (
37 {'id': 'audck', 'name': 'AUDCK', 'desc': 'AUD clock'},
38 {'id': 'naudsync', 'name': 'nAUDSYNC', 'desc': 'AUD sync'},
39 {'id': 'audata3', 'name': 'AUDATA3', 'desc': 'AUD data line 3'},
40 {'id': 'audata2', 'name': 'AUDATA2', 'desc': 'AUD data line 2'},
41 {'id': 'audata1', 'name': 'AUDATA1', 'desc': 'AUD data line 1'},
42 {'id': 'audata0', 'name': 'AUDATA0', 'desc': 'AUD data line 0'},
43 )
44 annotations = (
45 ('dest', 'Destination address'),
46 )
47
92b7b49f 48 def __init__(self):
10aeb8ea
GS
49 self.reset()
50
51 def reset(self):
e96593c1 52 self.ncnt = 0
53 self.nmax = 0
54 self.addr = 0
55 self.lastaddr = 0
e96593c1 56 self.ss = 0
57
58 def start(self):
59 self.out_ann = self.register(srd.OUTPUT_ANN)
60
61 def putx(self, data):
62 self.put(self.ss, self.samplenum, self.out_ann, data)
63
86e7c29c 64 def handle_clk_edge(self, clk, sync, datapins):
e96593c1 65 # Reconstruct nibble.
66 nib = 0
67 for i in range(4):
68 nib |= datapins[3-i] << i
69
70 # sync == 1: annotate if finished; update cmd.
71 # TODO: Annotate idle level (nibble = 0x03 && SYNC=1).
72 if sync == 1:
73 if (self.ncnt == self.nmax) and (self.nmax != 0):
74 # Done shifting an address: annotate.
75 self.putx([0, ['0x%08X' % self.addr]])
76 self.lastaddr = self.addr
77
78 self.ncnt = 0
79 self.addr = self.lastaddr
80 self.ss = self.samplenum
81 if nib == 0x08:
82 self.nmax = 1
83 elif nib == 0x09:
84 self.nmax = 2
85 elif nib == 0x0a:
86 self.nmax = 4
87 elif nib == 0x0b:
88 self.nmax = 8
89 else:
90 # Undefined or idle.
91 self.nmax = 0
92 else:
93 # sync == 0, valid cmd: start or continue shifting in nibbles.
94 if (self.nmax > 0):
95 # Clear tgt nibble.
96 self.addr &= ~(0x0F << (self.ncnt * 4))
97 # Set nibble.
98 self.addr |= nib << (self.ncnt * 4)
99 self.ncnt += 1
100
86e7c29c
UH
101 def decode(self):
102 while True:
103 pins = self.wait({0: 'r'})
e96593c1 104 clk = pins[0]
105 sync = pins[1]
106 d = pins[2:]
86e7c29c 107 self.handle_clk_edge(clk, sync, d)