]> sigrok.org Git - libsigrokdecode.git/blame - decoders/atsha204a/pd.py
atsha204a: Shorten output_tx_bytes()/output_rx_bytes() a bit.
[libsigrokdecode.git] / decoders / atsha204a / pd.py
CommitLineData
f96a9602
MP
1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2018 Michalis Pappas <mpappas@fastmail.fm>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, see <http://www.gnu.org/licenses/>.
18##
19
20import sigrokdecode as srd
21
22WORD_ADDR_RESET = 0x00
23WORD_ADDR_SLEEP = 0x01
24WORD_ADDR_IDLE = 0x02
25WORD_ADDR_COMMAND = 0x03
26
27WORD_ADDR = {0x00: 'RESET', 0x01: 'SLEEP', 0x02: 'IDLE', 0x03: 'COMMAND'}
28
29OPCODE_DERIVE_KEY = 0x1c
30OPCODE_DEV_REV = 0x30
31OPCODE_GEN_DIG = 0x15
32OPCODE_HMAC = 0x11
33OPCODE_CHECK_MAC = 0x28
34OPCODE_LOCK = 0x17
35OPCODE_MAC = 0x08
36OPCODE_NONCE = 0x16
37OPCODE_PAUSE = 0x01
38OPCODE_RANDOM = 0x1b
39OPCODE_READ = 0x02
40OPCODE_SHA = 0x47
41OPCODE_UPDATE_EXTRA = 0x20
42OPCODE_WRITE = 0x12
43
44OPCODES = {
45 0x01: 'Pause',
46 0x02: 'Read',
47 0x08: 'MAC',
48 0x11: 'HMAC',
49 0x12: 'Write',
50 0x15: 'GenDig',
51 0x16: 'Nonce',
52 0x17: 'Lock',
53 0x1b: 'Random',
54 0x1c: 'DeriveKey',
55 0x20: 'UpdateExtra',
56 0x28: 'CheckMac',
57 0x30: 'DevRev',
58 0x47: 'SHA',
59}
60
61ZONE_CONFIG = 0x00
62ZONE_OTP = 0x01
63ZONE_DATA = 0x02
64
65ZONES = {0x00: 'CONFIG', 0x01: 'OTP', 0x02: 'DATA'}
66
67STATUS_SUCCESS = 0x00
68STATUS_CHECKMAC_FAIL = 0x01
69STATUS_PARSE_ERROR = 0x03
70STATUS_EXECUTION_ERROR = 0x0f
71STATUS_READY = 0x11
72STATUS_CRC_COMM_ERROR = 0xff
73
74STATUS = {
75 0x00: 'Command success',
76 0x01: 'Checkmac failure',
77 0x03: 'Parse error',
78 0x0f: 'Execution error',
79 0x11: 'Ready',
80 0xff: 'CRC / communications error',
81}
82
83class Decoder(srd.Decoder):
84 api_version = 3
85 id = 'atsha204a'
86 name = 'ATSHA204A'
87 longname = 'Microchip ATSHA204A'
88 desc = 'Microchip ATSHA204A CryptoAuthentication device'
89 license = 'gplv2+'
90 inputs = ['i2c']
91 outputs = ['atsha204a']
92 annotations = (
93 ('waddr', 'Word address'),
94 ('count', 'Count'),
95 ('opcode', 'Opcode'),
96 ('param1', 'Param1'),
97 ('param2', 'Param2'),
98 ('data', 'Data'),
99 ('crc', 'CRC'),
100 ('status', 'Status'),
101 ('warning', 'Warning'),
102 )
103 annotation_rows = (
104 ('frame', 'Frame', (0, 1, 2, 3, 4, 5, 6)),
105 ('status', 'Status', (7,)),
106 ('warnings', 'Warnings', (8,)),
107 )
108
109 def __init__(self):
110 self.state = 'IDLE'
111 self.waddr = self.opcode = -1
112 self.ss_block = self.es_block = 0
113 self.bytes = []
114
115 def start(self):
116 self.out_ann = self.register(srd.OUTPUT_ANN)
117
118 def output_tx_bytes(self):
d6430dff
UH
119 b = self.bytes
120 if len(b) < 1: # Ignore wakeup.
f96a9602 121 return
d6430dff
UH
122 self.waddr = b[0][2]
123 self.display_waddr(b[0])
f96a9602 124 if self.waddr == WORD_ADDR_COMMAND:
d6430dff
UH
125 count = b[1][2]
126 self.display_count(b[1])
127 if len(b) - 1 != count:
128 self.display_warning(b[0][0], b[-1][1],
f96a9602 129 'Invalid frame length: Got {}, expecting {} '.format(
d6430dff 130 len(b) - 1, count))
f96a9602 131 return
d6430dff
UH
132 self.opcode = b[2][2]
133 self.display_opcode(b[2])
134 self.display_param1(b[3])
135 self.display_param2([b[4], b[5]])
136 self.display_data(b[6:-2])
137 self.display_crc([b[-2], b[-1]])
f96a9602
MP
138
139 def output_rx_bytes(self):
d6430dff
UH
140 b = self.bytes
141 count = b[0][2]
142 self.display_count(b[0])
f96a9602 143 if self.waddr == WORD_ADDR_RESET:
d6430dff
UH
144 self.display_data([b[1]])
145 self.display_crc([b[2], b[3]])
146 self.display_status(b[0][0], b[-1][1], b[1][2])
f96a9602
MP
147 elif self.waddr == WORD_ADDR_COMMAND:
148 if count == 4: # Status / Error.
d6430dff
UH
149 self.display_data([b[1]])
150 self.display_crc([b[2], b[3]])
151 self.display_status(b[0][0], b[-1][1], b[1][2])
f96a9602 152 else:
d6430dff
UH
153 self.display_data(b[1:-2])
154 self.display_crc([b[-2], b[-1]])
f96a9602
MP
155
156 def display_waddr(self, data):
157 self.put(data[0], data[1], self.out_ann, [0, ['Word addr: %s' % WORD_ADDR[data[2]]]])
158
159 def display_count(self, data):
160 self.put(data[0], data[1], self.out_ann, [1, ['Count: %s' % data[2]]])
161
162 def display_opcode(self, data):
163 self.put(data[0], data[1], self.out_ann, [2, ['Opcode: %s' % OPCODES[data[2]]]])
164
165 def display_param1(self, data):
166 if (self.opcode == OPCODE_CHECK_MAC) or (self.opcode == OPCODE_DEV_REV) or \
167 (self.opcode == OPCODE_HMAC) or (self.opcode == OPCODE_MAC) or \
168 (self.opcode == OPCODE_NONCE) or (self.opcode == OPCODE_RANDOM) or \
169 (self.opcode == OPCODE_SHA):
170 self.put(data[0], data[1], self.out_ann, [3, ['Mode: %02X' % data[2]]])
171 elif self.opcode == OPCODE_DERIVE_KEY:
172 self.put(data[0], data[1], self.out_ann, [3, ['Random: %s' % data[2]]])
173 elif self.opcode == OPCODE_GEN_DIG:
174 self.put(data[0], data[1], self.out_ann, [3, ['Zone: %s' % ZONES[data[2]]]])
175 elif self.opcode == OPCODE_LOCK:
176 self.put(data[0], data[1], self.out_ann, [3, ['Zone: {}, Summary: {}'.format(
177 'DATA/OTP' if data[2] else 'CONFIG',
178 'Ignored' if data[2] & 0x80 else 'Used')]])
179 elif self.opcode == OPCODE_PAUSE:
180 self.put(data[0], data[1], self.out_ann, [3, ['Selector: %02X' % data[2]]])
181 elif self.opcode == OPCODE_READ:
182 self.put(data[0], data[1], self.out_ann, [3, ['Zone: {}, Length: {}'.format(ZONES[data[2] & 0x03],
183 '32 bytes' if data[2] & 0x90 else '4 bytes')]])
184 elif self.opcode == OPCODE_WRITE:
185 self.put(data[0], data[1], self.out_ann, [3, ['Zone: {}, Encrypted: {}, Length: {}'.format(ZONES[data[2] & 0x03],
186 'Yes' if data[2] & 0x40 else 'No', '32 bytes' if data[2] & 0x90 else '4 bytes')]])
187 else:
188 self.put(data[0], data[1], self.out_ann, [3, ['Param1: %02X' % data[2]]])
189
190 def display_param2(self, data):
191 if self.opcode == OPCODE_DERIVE_KEY:
192 self.put(data[0][0], data[1][1], self.out_ann, [4, ['TargetKey: {:02x} {:02x}'.format(data[1][2], data[0][2])]])
193 elif (self.opcode == OPCODE_NONCE) or (self.opcode == OPCODE_PAUSE) or (self.opcode == OPCODE_RANDOM):
194 self.put(data[0][0], data[1][1], self.out_ann, [4, ['Zero: {:02x} {:02x}'.format(data[1][2], data[0][2])]])
195 elif (self.opcode == OPCODE_HMAC) or (self.opcode == OPCODE_MAC) or \
196 (self.opcode == OPCODE_CHECK_MAC) or (self.opcode == OPCODE_GEN_DIG):
197 self.put(data[0][0], data[1][1], self.out_ann, [4, ['SlotID: {:02x} {:02x}'.format(data[1][2], data[0][2])]])
198 elif self.opcode == OPCODE_LOCK:
199 self.put(data[0][0], data[1][1], self.out_ann, [4, ['Summary: {:02x} {:02x}'.format(data[1][2], data[0][2])]])
200 elif (self.opcode == OPCODE_READ) or (self.opcode == OPCODE_WRITE):
201 self.put(data[0][0], data[1][1], self.out_ann, [4, ['Address: {:02x} {:02x}'.format(data[1][2], data[0][2])]])
202 elif self.opcode == OPCODE_UPDATE_EXTRA:
203 self.put(data[0][0], data[1][1], self.out_ann, [4, ['NewValue: {:02x}'.format(data[0][2])]])
204 else:
205 self.put(data[0][0], data[1][1], self.out_ann, [4, ['-']])
206
207 def display_data(self, data):
208 if len(data) == 0:
209 return
210 if self.opcode == OPCODE_CHECK_MAC:
211 self.put(data[0][0], data[31][1], self.out_ann, [5, ['ClientChal: %s' % ' '.join(format(i[2], '02x') for i in data[0:31])]])
212 self.put(data[32][0], data[63][1], self.out_ann, [5, ['ClientResp: %s' % ' '.join(format(i[2], '02x') for i in data[32:63])]])
213 self.put(data[64][0], data[76][1], self.out_ann, [5, ['OtherData: %s' % ' '.join(format(i[2], '02x') for i in data[64:76])]])
214 elif self.opcode == OPCODE_DERIVE_KEY:
215 self.put(data[0][0], data[31][1], self.out_ann, [5, ['MAC: %s' % ' '.join(format(i[2], '02x') for i in data)]])
216 elif self.opcode == OPCODE_GEN_DIG:
217 self.put(data[0][0], data[3][1], self.out_ann, [5, ['OtherData: %s' % ' '.join(format(i[2], '02x') for i in data)]])
218 elif self.opcode == OPCODE_MAC:
219 self.put(data[0][0], data[31][1], self.out_ann, [5, ['Challenge: %s' % ' '.join(format(i[2], '02x') for i in data)]])
220 elif self.opcode == OPCODE_WRITE:
221 if len(data) > 32: # Value + MAC.
222 self.put(data[0][0], data[-31][1], self.out_ann, [5, ['Value: %s' % ' '.join(format(i[2], '02x') for i in data)]])
223 self.put(data[-32][0], data[-1][1], self.out_ann, [5, ['MAC: %s' % ' '.join(format(i[2], '02x') for i in data)]])
224 else: # Just value.
225 self.put(data[0][0], data[-1][1], self.out_ann, [5, ['Value: %s' % ' '.join(format(i[2], '02x') for i in data)]])
226 else:
227 self.put(data[0][0], data[-1][1], self.out_ann, [5, ['Data: %s' % ' '.join(format(i[2], '02x') for i in data)]])
228
229 def display_crc(self, data):
230 self.put(data[0][0], data[1][1], self.out_ann, [6, ['CRC: {:02X} {:02X}'.format(data[0][2], data[1][2])]])
231
232 def display_status(self, start, end, status):
233 self.put(start, end, self.out_ann, [7, ['Status: %s' % STATUS[status]]])
234
235 def display_warning(self, start, end, msg):
236 self.put(start, end, self.out_ann, [8, ['Warning: %s' % msg]])
237
238 def decode(self, ss, es, data):
239 cmd, databyte = data
240
241 # State machine.
242 if self.state == 'IDLE':
243 # Wait for an I²C START condition.
244 if cmd != 'START':
245 return
246 self.state = 'GET SLAVE ADDR'
247 self.ss_block = ss
248 elif self.state == 'GET SLAVE ADDR':
249 # Wait for an address read/write operation.
250 if cmd == 'ADDRESS READ':
251 self.state = 'READ REGS'
252 elif cmd == 'ADDRESS WRITE':
253 self.state = 'WRITE REGS'
254 elif self.state == 'READ REGS':
255 if cmd == 'DATA READ':
256 self.bytes.append([ss, es, databyte])
257 elif cmd == 'STOP':
258 self.es_block = es
259 # Reset the opcode before received data, as this causes
260 # responses to be displayed incorrectly.
261 self.opcode = -1
262 self.output_rx_bytes()
263 self.waddr = -1
264 self.bytes = []
265 self.state = 'IDLE'
266 elif self.state == 'WRITE REGS':
267 if cmd == 'DATA WRITE':
268 self.bytes.append([ss, es, databyte])
269 elif cmd == 'STOP':
270 self.es_block = es
271 self.output_tx_bytes()
272 self.bytes = []
273 self.state = 'IDLE'
274