[libsigrokdecode.git] / decoders / adxl345 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2020 Analog Devices Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 3 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import sigrokdecode as srd
from common.srdhelper import SrdIntEnum
from .lists import *

WORD_SIZE = 8

class Channel():
    MISO, MOSI = range(2)

class Operation():
    READ, WRITE = range(2)

class BitType():
    ENABLE = {1: ['Enable %s', 'En %s', '%s '], 0: ['Disable %s', 'Dis %s', '!%s '],}
    SOURCE = {1: ['Involve %s', 'Inv %s', '%s'], 0: ['Not involve %s', 'Not inv %s', '!%s'],}
    INTERRUPT = {1: ['INT2 %s', 'I2: %s '], 0: ['INT1 %s', 'I1:%s '],}
    AC_DC = {1: ['%s ac', 'ac'], 0: ['%s dc', 'dc'],}
    UNUSED = {1: ['N/A'], 0: ['N/A'],}
    OTHER = 0

class Bit():
    def __init__(self, name, type, values=None):
        self.value = 0
        self.name = name
        self.type = type
        self.values = values

    def set_value(self, value):
        self.value = value

    def get_bit_annotation(self):
        if self.type == BitType.OTHER:
            annotation = self.values[self.value].copy()
        else:
            annotation = self.type[self.value].copy()

        for index in range(len(annotation)):
            if '%s' in annotation[index]:
                annotation[index] = str(annotation[index] % self.name)
        return annotation

Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING')

class Decoder(srd.Decoder):
    api_version = 3
    id = 'adxl345'
    name = 'ADXL345'
    longname = 'Analog Devices ADXL345'
    desc = 'Analog Devices ADXL345 3-axis accelerometer.'
    license = 'gplv2+'
    inputs = ['spi']
    outputs = []
    tags = ['IC', 'Sensor']
    annotations = (
        ('read', 'Read'),
        ('write', 'Write'),
        ('mb', 'Multiple bytes'),
        ('reg-address', 'Register address'),
        ('reg-data', 'Register data'),
        ('warning', 'Warning'),
    )
    annotation_rows = (
        ('reg', 'Registers', (Ann.READ, Ann.WRITE, Ann.MB, Ann.REG_ADDRESS)),
        ('data', 'Data', (Ann.REG_DATA, Ann.WARNING)),
    )

    def __init__(self):
        self.reset()

    def reset(self):
        self.mosi, self.miso = [], []
        self.reg = []
        self.operation = None
        self.address = 0
        self.data = -1
        self.state = 'IDLE'
        self.ss, self.es = -1, -1
        self.samples_per_bit = 0

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putb(self, data, index):
        start = self.ss + (self.samples_per_bit * index)
        self.put(start, start + self.samples_per_bit, self.out_ann, data)

    def putbs(self, data, start_index, stop_index):
        start_index = self.reverse_bit_index(start_index, WORD_SIZE)
        stop_index = self.reverse_bit_index(stop_index, WORD_SIZE)
        start = self.ss + (self.samples_per_bit * start_index)
        stop = start + (self.samples_per_bit * (stop_index - start_index + 1))
        self.put(start, stop, self.out_ann, data)

    def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg):
        if data == 0 and error_msg is not None:
            self.putx([Ann.WARNING, error_msg])
        else:
            result = (data * factor) / 1000
            self.putx([Ann.REG_DATA, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]])

    def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg):
        self.putb([Ann.REG_DATA, [en_msg if bit else dis_msg]], index)

    def interpret_bits(self, data, bits):
        bits_values = []
        for offset in range(8):
            bits_values.insert(0, (data & (1 << offset)) >> offset)

        for index in range(len(bits)):
            if bits[index] is None:
                continue
            bit = bits[index]
            bit.set_value(bits_values[index])
            self.putb([Ann.REG_DATA, bit.get_bit_annotation()], index)

        return list(reversed(bits_values))

    def reverse_bit_index(self, index, word_size):
        return word_size - index - 1

    def get_decimal_number(self, bits, start_index, stop_index):
        number = 0
        interval = range(start_index, stop_index + 1, 1)
        for index, offset in zip(interval, range(len(interval))):
            bit = bits[index]
            number = number | (bit << offset)
        return number

    def get_axis_value(self, data, axis):
        if self.data != - 1:
            data <<= 8
            self.data |= data
            self.put(self.start_index, self.es, self.out_ann,
                [Ann.REG_DATA, ['%s: 0x%04X' % (axis, self.data), str(data)]])
            self.data = -1
        else:
            self.putx([Ann.REG_DATA, [str(data)]])

    def handle_reg_0x1D(self, data):
        self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
            error_messages['undesirable'])

    def handle_reg_0x1E(self, data):
        self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)

    def handle_reg_0x1F(self, data):
        self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)

    def handle_reg_0x20(self, data):
        self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)

    def handle_reg_0x21(self, data):
        self.handle_reg_with_scaling_factor(data, 0.625, 'Time', 's',
            error_messages['dis_single_double'])

    def handle_reg_0x22(self, data):
        self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
            error_messages['dis_double'])

    def handle_reg_0x23(self, data):
        self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
            error_messages['dis_double'])

    def handle_reg_0x24(self, data):
        self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's',
            error_messages['undesirable'])

    def handle_reg_0x25(self, data):
        self.handle_reg_0x1D(data)

    def handle_reg_0x26(self, data):
        self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
            error_messages['interrupt'])

    def handle_reg_0x27(self, data):
        bits = [Bit('ACT', BitType.AC_DC),
                Bit('ACT_X', BitType.ENABLE),
                Bit('ACT_Y', BitType.ENABLE),
                Bit('ACT_Z', BitType.ENABLE),
                Bit('INACT', BitType.AC_DC),
                Bit('INACT_X', BitType.ENABLE),
                Bit('INACT_Y', BitType.ENABLE),
                Bit('INACT_Z', BitType.ENABLE)]
        self.interpret_bits(data, bits)

    def handle_reg_0x28(self, data):
        self.handle_reg_0x1D(data)

    def handle_reg_0x29(self, data):
        self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
            error_messages['undesirable'])

    def handle_reg_0x2A(self, data):
        bits = [Bit('', BitType.UNUSED),
                Bit('', BitType.UNUSED),
                Bit('', BitType.UNUSED),
                Bit('', BitType.UNUSED),
                Bit('', BitType.OTHER, {1: ['Suppressed', 'Suppr', 'S'],
                    0: ['Unsuppressed', 'Unsuppr', 'Uns'],}),
                Bit('TAP_X', BitType.ENABLE),
                Bit('TAP_Y', BitType.ENABLE),
                Bit('TAP_Z', BitType.ENABLE)]
        self.interpret_bits(data, bits)

    def handle_reg_0x2B(self, data):
        bits = [Bit('', BitType.UNUSED),
                Bit('ACT_X', BitType.SOURCE),
                Bit('ACT_Y', BitType.SOURCE),
                Bit('ACT_Z', BitType.SOURCE),
                Bit('', BitType.OTHER, {1: ['Asleep', 'Asl'],
                    0: ['Not asleep', 'Not asl', '!Asl'],}),
                Bit('TAP_X', BitType.SOURCE),
                Bit('TAP_Y', BitType.SOURCE),
                Bit('TAP_Z', BitType.SOURCE)]
        self.interpret_bits(data, bits)

    def handle_reg_0x2C(self, data):
        bits = [Bit('', BitType.UNUSED),
                Bit('', BitType.UNUSED),
                Bit('', BitType.UNUSED),
                Bit('', BitType.OTHER, {1: ['Reduce power', 'Reduce pw', 'Red pw'], 0: ['Normal operation', 'Normal op', 'Norm op'],})]
        bits_values = self.interpret_bits(data, bits)

        start_index, stop_index = 0, 3
        rate = self.get_decimal_number(bits_values, start_index, start_index)
        self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index)

    def handle_reg_0x2D(self, data):
        bits = [Bit('', BitType.UNUSED),
                Bit('', BitType.UNUSED),
                Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
                Bit('AUTO_SLEEP', BitType.ENABLE),
                Bit('', BitType.OTHER, {1: ['Measurement mode', 'Measurement', 'Meas'], 0: ['Standby mode', 'Standby'], }),
                Bit('', BitType.OTHER, {1: ['Sleep mode', 'Sleep', 'Slp'], 0: ['Normal mode', 'Normal', 'Nrm'],})]
        bits_values = self.interpret_bits(data, bits)

        start_index, stop_index = 0, 1
        wakeup = self.get_decimal_number(bits_values, start_index, stop_index)
        frequency = 2 ** (~wakeup & 0x03)
        self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index)

    def handle_reg_0x2E(self, data):
        bits = [Bit('DATA_READY', BitType.ENABLE),
                Bit('SINGLE_TAP', BitType.ENABLE),
                Bit('DOUBLE_TAP', BitType.ENABLE),
                Bit('Activity', BitType.ENABLE),
                Bit('Inactivity', BitType.ENABLE),
                Bit('FREE_FALL', BitType.ENABLE),
                Bit('Watermark', BitType.ENABLE),
                Bit('Overrun', BitType.ENABLE)]
        self.interpret_bits(data, bits)

    def handle_reg_0x2F(self, data):
        bits = [Bit('DATA_READY', BitType.INTERRUPT),
                Bit('SINGLE_TAP', BitType.INTERRUPT),
                Bit('DOUBLE_TAP', BitType.INTERRUPT),
                Bit('Activity', BitType.INTERRUPT),
                Bit('Inactivity', BitType.INTERRUPT),
                Bit('FREE_FALL', BitType.INTERRUPT),
                Bit('Watermark', BitType.INTERRUPT),
                Bit('Overrun', BitType.INTERRUPT)]
        self.interpret_bits(data, bits)

    def handle_reg_0x30(self, data):
        bits = [Bit('DATA_READY', BitType.SOURCE),
                Bit('SINGLE_TAP', BitType.SOURCE),
                Bit('DOUBLE_TAP', BitType.SOURCE),
                Bit('Activity', BitType.SOURCE),
                Bit('Inactivity', BitType.SOURCE),
                Bit('FREE_FALL', BitType.SOURCE),
                Bit('Watermark', BitType.SOURCE),
                Bit('Overrun', BitType.SOURCE)]
        self.interpret_bits(data, bits)

    def handle_reg_0x31(self, data):
        bits = [Bit('SELF_TEST', BitType.ENABLE),
                Bit('', BitType.OTHER, {1: ['3-wire SPI', '3-SPI'], 0: ['4-wire SPI', '4-SPI'],}),
                Bit('', BitType.OTHER, {1: ['INT ACT LOW', 'INT LOW'], 0: ['INT ACT HIGH', 'INT HIGH'],}),
                Bit('', BitType.UNUSED),
                Bit('', BitType.OTHER, {1: ['Full resolution', 'Full res'], 0: ['10-bit mode', '10-bit'],}),
                Bit('', BitType.OTHER, {1: ['MSB mode', 'MSB'], 0: ['LSB mode', 'LSB'],})]
        bits_values = self.interpret_bits(data, bits)

        start_index, stop_index = 0, 1
        range_g = self.get_decimal_number(bits_values, start_index, stop_index)
        result = 2 ** (range_g + 1)
        self.putbs([Ann.REG_DATA, ['+/-%d g' % result]], stop_index, start_index)

    def handle_reg_0x32(self, data):
        self.data = data
        self.putx([Ann.REG_DATA, [str(data)]])

    def handle_reg_0x33(self, data):
        self.get_axis_value(data, 'X')

    def handle_reg_0x34(self, data):
        self.handle_reg_0x32(data)

    def handle_reg_0x35(self, data):
        self.get_axis_value(data, 'Y')

    def handle_reg_0x36(self, data):
        self.handle_reg_0x32(data)

    def handle_reg_0x37(self, data):
        self.get_axis_value(data, 'Z')

    def handle_reg_0x38(self, data):
        bits = [None,
                None,
                Bit('', BitType.OTHER, {1: ['Trig-INT2', 'INT2'], 0: ['Trig-INT1', 'INT1'], })]
        bits_values = self.interpret_bits(data, bits)

        start_index, stop_index = 6, 7
        fifo = self.get_decimal_number(bits_values, start_index, stop_index)
        self.putbs([Ann.REG_DATA, [fifo_modes[fifo]]], stop_index, start_index)

        start_index, stop_index = 0, 4
        samples = self.get_decimal_number(bits_values, start_index, stop_index)
        self.putbs([Ann.REG_DATA, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index)

    def handle_reg_0x39(self, data):
        bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}),
                Bit('', BitType.UNUSED)]
        bits_values = self.interpret_bits(data, bits)

        start_index, stop_index = 0, 5
        entries = self.get_decimal_number(bits_values, start_index, stop_index)
        self.putbs([Ann.REG_DATA, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index)

    def get_bit(self, channel):
        if (channel == Channel.MOSI and self.mosi is None) or \
                (channel == Channel.MISO and self.miso is None):
            raise Exception('No available data')

        mosi_bit, miso_bit = 0, 0
        if self.miso is not None:
            if len(self.mosi) < 0:
                raise Exception('No available data')
            miso_bit = self.miso.pop(0)
        if self.miso is not None:
            if len(self.miso) < 0:
                raise Exception('No available data')
            mosi_bit = self.mosi.pop(0)

        if channel == Channel.MOSI:
            return mosi_bit
        return miso_bit

    def decode(self, ss, es, data):
        ptype = data[0]

        if ptype == 'CS-CHANGE':
            cs_old, cs_new = data[1:]
            if cs_old is not None and cs_old == 1 and cs_new == 0:
                self.ss, self.es = ss, es
                self.state = 'ADDRESS-BYTE'
            else:
                self.state = 'IDLE'

        elif ptype == 'BITS':
            if data[1] is not None:
                self.mosi = list(reversed(data[1]))
            if data[2] is not None:
                self.miso = list(reversed(data[2]))

            if self.mosi is None and self.miso is None:
                return

            if self.state == 'ADDRESS-BYTE':
                # OPERATION BIT
                op_bit = self.get_bit(Channel.MOSI)
                self.put(op_bit[1], op_bit[2], self.out_ann,
                    [Ann.READ if op_bit[0] else Ann.WRITE, operations[op_bit[0]]])
                self.operation = Operation.READ if op_bit[0] else Operation.WRITE
                # MULTIPLE-BYTE BIT
                mb_bit = self.get_bit(Channel.MOSI)
                self.put(mb_bit[1], mb_bit[2], self.out_ann, [Ann.MB, number_bytes[mb_bit[0]]])

                # REGISTER 6-BIT ADDRESS
                self.address = 0
                start_sample = self.mosi[0][1]
                addr_bit = []
                for i in range(6):
                    addr_bit = self.get_bit(Channel.MOSI)
                    self.address |= addr_bit[0]
                    self.address <<= 1
                self.address >>= 1
                self.put(start_sample, addr_bit[2], self.out_ann,
                    [Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X'
                    % self.address, '0x%02X' % self.address]])
                self.ss = -1
                self.state = 'DATA'

            elif self.state == 'DATA':
                self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)

                self.mosi, self.miso = [], []
                if self.ss == -1:
                    self.ss, self.es = self.reg[0][1], es
                    self.samples_per_bit = self.reg[0][2] - self.ss

                if len(self.reg) < 8:
                    return
                else:
                    reg_value = 0
                    reg_bit = []
                    for offset in range(7, -1, -1):
                        reg_bit = self.reg.pop(0)

                        mask = reg_bit[0] << offset
                        reg_value |= mask

                    if self.address < 0x00 or self.address > 0x39:
                        return

                    if self.address in [0x32, 0x34, 0x36]:
                        self.start_index = self.ss

                    if 0x1D > self.address >= 0x00:
                        self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, [str(self.address)]])
                        self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]])
                    else:
                        self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]])
                        handle_reg = getattr(self, 'handle_reg_0x%02X' % self.address)
                        handle_reg(reg_value)

                    self.reg = []
                    self.address += 1
                    self.ss = -1
Commit	Line	Data
f47d3a2d TP	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2020 Analog Devices Inc.
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 3 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	##
	19
	20	import sigrokdecode as srd
7b0f3c78	21	from common.srdhelper import SrdIntEnum
f47d3a2d TP	22	from .lists import *
	23
	24	WORD_SIZE = 8
	25
	26	class Channel():
88098c75	27	MISO, MOSI = range(2)
f47d3a2d TP	28
f47d3a2d TP	29	class Operation():
88098c75	30	READ, WRITE = range(2)
f47d3a2d TP	31
	32	class BitType():
	33	ENABLE = {1: ['Enable %s', 'En %s', '%s '], 0: ['Disable %s', 'Dis %s', '!%s '],}
	34	SOURCE = {1: ['Involve %s', 'Inv %s', '%s'], 0: ['Not involve %s', 'Not inv %s', '!%s'],}
	35	INTERRUPT = {1: ['INT2 %s', 'I2: %s '], 0: ['INT1 %s', 'I1:%s '],}
	36	AC_DC = {1: ['%s ac', 'ac'], 0: ['%s dc', 'dc'],}
	37	UNUSED = {1: ['N/A'], 0: ['N/A'],}
	38	OTHER = 0
	39
	40	class Bit():
	41	def __init__(self, name, type, values=None):
	42	self.value = 0
	43	self.name = name
	44	self.type = type
	45	self.values = values
	46
	47	def set_value(self, value):
	48	self.value = value
	49
	50	def get_bit_annotation(self):
	51	if self.type == BitType.OTHER:
	52	annotation = self.values[self.value].copy()
	53	else:
	54	annotation = self.type[self.value].copy()
	55
	56	for index in range(len(annotation)):
	57	if '%s' in annotation[index]:
	58	annotation[index] = str(annotation[index] % self.name)
	59	return annotation
	60
7b0f3c78 UH	61	Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING')
7b0f3c78 UH	62
f47d3a2d TP	63	class Decoder(srd.Decoder):
	64	api_version = 3
	65	id = 'adxl345'
	66	name = 'ADXL345'
	67	longname = 'Analog Devices ADXL345'
	68	desc = 'Analog Devices ADXL345 3-axis accelerometer.'
	69	license = 'gplv2+'
	70	inputs = ['spi']
	71	outputs = []
	72	tags = ['IC', 'Sensor']
	73	annotations = (
	74	('read', 'Read'),
	75	('write', 'Write'),
	76	('mb', 'Multiple bytes'),
	77	('reg-address', 'Register address'),
	78	('reg-data', 'Register data'),
	79	('warning', 'Warning'),
	80	)
	81	annotation_rows = (
7b0f3c78 UH	82	('reg', 'Registers', (Ann.READ, Ann.WRITE, Ann.MB, Ann.REG_ADDRESS)),
7b0f3c78 UH	83	('data', 'Data', (Ann.REG_DATA, Ann.WARNING)),
f47d3a2d TP	84	)
	85
	86	def __init__(self):
	87	self.reset()
	88
	89	def reset(self):
88098c75	90	self.mosi, self.miso = [], []
f47d3a2d TP	91	self.reg = []
	92	self.operation = None
	93	self.address = 0
	94	self.data = -1
	95	self.state = 'IDLE'
88098c75	96	self.ss, self.es = -1, -1
f47d3a2d TP	97	self.samples_per_bit = 0
	98
	99	def start(self):
	100	self.out_ann = self.register(srd.OUTPUT_ANN)
	101
	102	def putx(self, data):
	103	self.put(self.ss, self.es, self.out_ann, data)
	104
	105	def putb(self, data, index):
	106	start = self.ss + (self.samples_per_bit * index)
	107	self.put(start, start + self.samples_per_bit, self.out_ann, data)
	108
	109	def putbs(self, data, start_index, stop_index):
4b0d57fc UH	110	start_index = self.reverse_bit_index(start_index, WORD_SIZE)
4b0d57fc UH	111	stop_index = self.reverse_bit_index(stop_index, WORD_SIZE)
f47d3a2d TP	112	start = self.ss + (self.samples_per_bit * start_index)
	113	stop = start + (self.samples_per_bit * (stop_index - start_index + 1))
	114	self.put(start, stop, self.out_ann, data)
	115
	116	def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg):
	117	if data == 0 and error_msg is not None:
7b0f3c78	118	self.putx([Ann.WARNING, error_msg])
f47d3a2d TP	119	else:
f47d3a2d TP	120	result = (data * factor) / 1000
7b0f3c78	121	self.putx([Ann.REG_DATA, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]])
f47d3a2d TP	122
f47d3a2d TP	123	def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg):
7b0f3c78	124	self.putb([Ann.REG_DATA, [en_msg if bit else dis_msg]], index)
f47d3a2d TP	125
	126	def interpret_bits(self, data, bits):
	127	bits_values = []
	128	for offset in range(8):
	129	bits_values.insert(0, (data & (1 << offset)) >> offset)
	130
	131	for index in range(len(bits)):
	132	if bits[index] is None:
	133	continue
	134	bit = bits[index]
	135	bit.set_value(bits_values[index])
7b0f3c78	136	self.putb([Ann.REG_DATA, bit.get_bit_annotation()], index)
f47d3a2d TP	137
	138	return list(reversed(bits_values))
	139
	140	def reverse_bit_index(self, index, word_size):
	141	return word_size - index - 1
	142
	143	def get_decimal_number(self, bits, start_index, stop_index):
	144	number = 0
	145	interval = range(start_index, stop_index + 1, 1)
	146	for index, offset in zip(interval, range(len(interval))):
	147	bit = bits[index]
	148	number = number \| (bit << offset)
	149	return number
	150
	151	def get_axis_value(self, data, axis):
	152	if self.data != - 1:
	153	data <<= 8
	154	self.data \|= data
	155	self.put(self.start_index, self.es, self.out_ann,
7b0f3c78	156	[Ann.REG_DATA, ['%s: 0x%04X' % (axis, self.data), str(data)]])
f47d3a2d TP	157	self.data = -1
f47d3a2d TP	158	else:
7b0f3c78	159	self.putx([Ann.REG_DATA, [str(data)]])
f47d3a2d TP	160
	161	def handle_reg_0x1D(self, data):
	162	self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
	163	error_messages['undesirable'])
	164
	165	def handle_reg_0x1E(self, data):
	166	self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)
	167
	168	def handle_reg_0x1F(self, data):
	169	self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)
	170
	171	def handle_reg_0x20(self, data):
	172	self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)
	173
	174	def handle_reg_0x21(self, data):
	175	self.handle_reg_with_scaling_factor(data, 0.625, 'Time', 's',
	176	error_messages['dis_single_double'])
	177
	178	def handle_reg_0x22(self, data):
81bf080f	179	self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
f47d3a2d TP	180	error_messages['dis_double'])
	181
	182	def handle_reg_0x23(self, data):
	183	self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
	184	error_messages['dis_double'])
	185
	186	def handle_reg_0x24(self, data):
	187	self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's',
	188	error_messages['undesirable'])
	189
	190	def handle_reg_0x25(self, data):
	191	self.handle_reg_0x1D(data)
	192
	193	def handle_reg_0x26(self, data):
	194	self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
	195	error_messages['interrupt'])
	196
	197	def handle_reg_0x27(self, data):
	198	bits = [Bit('ACT', BitType.AC_DC),
	199	Bit('ACT_X', BitType.ENABLE),
	200	Bit('ACT_Y', BitType.ENABLE),
	201	Bit('ACT_Z', BitType.ENABLE),
	202	Bit('INACT', BitType.AC_DC),
	203	Bit('INACT_X', BitType.ENABLE),
	204	Bit('INACT_Y', BitType.ENABLE),
	205	Bit('INACT_Z', BitType.ENABLE)]
	206	self.interpret_bits(data, bits)
	207
	208	def handle_reg_0x28(self, data):
	209	self.handle_reg_0x1D(data)
	210
	211	def handle_reg_0x29(self, data):
	212	self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
	213	error_messages['undesirable'])
	214
	215	def handle_reg_0x2A(self, data):
	216	bits = [Bit('', BitType.UNUSED),
	217	Bit('', BitType.UNUSED),
	218	Bit('', BitType.UNUSED),
	219	Bit('', BitType.UNUSED),
	220	Bit('', BitType.OTHER, {1: ['Suppressed', 'Suppr', 'S'],
	221	0: ['Unsuppressed', 'Unsuppr', 'Uns'],}),
	222	Bit('TAP_X', BitType.ENABLE),
	223	Bit('TAP_Y', BitType.ENABLE),
	224	Bit('TAP_Z', BitType.ENABLE)]
	225	self.interpret_bits(data, bits)
	226
	227	def handle_reg_0x2B(self, data):
	228	bits = [Bit('', BitType.UNUSED),
	229	Bit('ACT_X', BitType.SOURCE),
	230	Bit('ACT_Y', BitType.SOURCE),
	231	Bit('ACT_Z', BitType.SOURCE),
	232	Bit('', BitType.OTHER, {1: ['Asleep', 'Asl'],
	233	0: ['Not asleep', 'Not asl', '!Asl'],}),
	234	Bit('TAP_X', BitType.SOURCE),
	235	Bit('TAP_Y', BitType.SOURCE),
	236	Bit('TAP_Z', BitType.SOURCE)]
	237	self.interpret_bits(data, bits)
	238
	239	def handle_reg_0x2C(self, data):
	240	bits = [Bit('', BitType.UNUSED),
	241	Bit('', BitType.UNUSED),
	242	Bit('', BitType.UNUSED),
	243	Bit('', BitType.OTHER, {1: ['Reduce power', 'Reduce pw', 'Red pw'], 0: ['Normal operation', 'Normal op', 'Norm op'],})]
244	bits_values = self.interpret_bits(data, bits)
245
88098c75	246	start_index, stop_index = 0, 3
f47d3a2d	247	rate = self.get_decimal_number(bits_values, start_index, start_index)
7b0f3c78	248	self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index)
f47d3a2d TP	249
	250	def handle_reg_0x2D(self, data):
	251	bits = [Bit('', BitType.UNUSED),
	252	Bit('', BitType.UNUSED),
	253	Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
	254	Bit('AUTO_SLEEP', BitType.ENABLE),
	255	Bit('', BitType.OTHER, {1: ['Measurement mode', 'Measurement', 'Meas'], 0: ['Standby mode', 'Standby'], }),
	256	Bit('', BitType.OTHER, {1: ['Sleep mode', 'Sleep', 'Slp'], 0: ['Normal mode', 'Normal', 'Nrm'],})]
	257	bits_values = self.interpret_bits(data, bits)
	258
88098c75	259	start_index, stop_index = 0, 1
f47d3a2d TP	260	wakeup = self.get_decimal_number(bits_values, start_index, stop_index)
f47d3a2d TP	261	frequency = 2 ** (~wakeup & 0x03)
7b0f3c78	262	self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index)
f47d3a2d TP	263
	264	def handle_reg_0x2E(self, data):
	265	bits = [Bit('DATA_READY', BitType.ENABLE),
	266	Bit('SINGLE_TAP', BitType.ENABLE),
	267	Bit('DOUBLE_TAP', BitType.ENABLE),
	268	Bit('Activity', BitType.ENABLE),
	269	Bit('Inactivity', BitType.ENABLE),
	270	Bit('FREE_FALL', BitType.ENABLE),
	271	Bit('Watermark', BitType.ENABLE),
	272	Bit('Overrun', BitType.ENABLE)]
	273	self.interpret_bits(data, bits)
	274
	275	def handle_reg_0x2F(self, data):
	276	bits = [Bit('DATA_READY', BitType.INTERRUPT),
	277	Bit('SINGLE_TAP', BitType.INTERRUPT),
	278	Bit('DOUBLE_TAP', BitType.INTERRUPT),
	279	Bit('Activity', BitType.INTERRUPT),
	280	Bit('Inactivity', BitType.INTERRUPT),
	281	Bit('FREE_FALL', BitType.INTERRUPT),
	282	Bit('Watermark', BitType.INTERRUPT),
	283	Bit('Overrun', BitType.INTERRUPT)]
	284	self.interpret_bits(data, bits)
	285
	286	def handle_reg_0x30(self, data):
	287	bits = [Bit('DATA_READY', BitType.SOURCE),
	288	Bit('SINGLE_TAP', BitType.SOURCE),
	289	Bit('DOUBLE_TAP', BitType.SOURCE),
	290	Bit('Activity', BitType.SOURCE),
	291	Bit('Inactivity', BitType.SOURCE),
	292	Bit('FREE_FALL', BitType.SOURCE),
	293	Bit('Watermark', BitType.SOURCE),
	294	Bit('Overrun', BitType.SOURCE)]
	295	self.interpret_bits(data, bits)
	296
	297	def handle_reg_0x31(self, data):
	298	bits = [Bit('SELF_TEST', BitType.ENABLE),
	299	Bit('', BitType.OTHER, {1: ['3-wire SPI', '3-SPI'], 0: ['4-wire SPI', '4-SPI'],}),
	300	Bit('', BitType.OTHER, {1: ['INT ACT LOW', 'INT LOW'], 0: ['INT ACT HIGH', 'INT HIGH'],}),
	301	Bit('', BitType.UNUSED),
	302	Bit('', BitType.OTHER, {1: ['Full resolution', 'Full res'], 0: ['10-bit mode', '10-bit'],}),
	303	Bit('', BitType.OTHER, {1: ['MSB mode', 'MSB'], 0: ['LSB mode', 'LSB'],})]
	304	bits_values = self.interpret_bits(data, bits)
	305
88098c75	306	start_index, stop_index = 0, 1
f47d3a2d TP	307	range_g = self.get_decimal_number(bits_values, start_index, stop_index)
f47d3a2d TP	308	result = 2 ** (range_g + 1)
7b0f3c78	309	self.putbs([Ann.REG_DATA, ['+/-%d g' % result]], stop_index, start_index)
f47d3a2d TP	310
	311	def handle_reg_0x32(self, data):
	312	self.data = data
7b0f3c78	313	self.putx([Ann.REG_DATA, [str(data)]])
f47d3a2d TP	314
	315	def handle_reg_0x33(self, data):
	316	self.get_axis_value(data, 'X')
	317
	318	def handle_reg_0x34(self, data):
	319	self.handle_reg_0x32(data)
	320
	321	def handle_reg_0x35(self, data):
	322	self.get_axis_value(data, 'Y')
	323
	324	def handle_reg_0x36(self, data):
	325	self.handle_reg_0x32(data)
	326
	327	def handle_reg_0x37(self, data):
	328	self.get_axis_value(data, 'Z')
	329
	330	def handle_reg_0x38(self, data):
	331	bits = [None,
	332	None,
	333	Bit('', BitType.OTHER, {1: ['Trig-INT2', 'INT2'], 0: ['Trig-INT1', 'INT1'], })]
	334	bits_values = self.interpret_bits(data, bits)
	335
88098c75	336	start_index, stop_index = 6, 7
f47d3a2d	337	fifo = self.get_decimal_number(bits_values, start_index, stop_index)
7b0f3c78	338	self.putbs([Ann.REG_DATA, [fifo_modes[fifo]]], stop_index, start_index)
f47d3a2d	339
88098c75	340	start_index, stop_index = 0, 4
f47d3a2d	341	samples = self.get_decimal_number(bits_values, start_index, stop_index)
7b0f3c78	342	self.putbs([Ann.REG_DATA, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index)
f47d3a2d TP	343
	344	def handle_reg_0x39(self, data):
	345	bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}),
	346	Bit('', BitType.UNUSED)]
	347	bits_values = self.interpret_bits(data, bits)
	348
88098c75	349	start_index, stop_index = 0, 5
f47d3a2d	350	entries = self.get_decimal_number(bits_values, start_index, stop_index)
7b0f3c78	351	self.putbs([Ann.REG_DATA, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index)
f47d3a2d TP	352
	353	def get_bit(self, channel):
	354	if (channel == Channel.MOSI and self.mosi is None) or \
	355	(channel == Channel.MISO and self.miso is None):
	356	raise Exception('No available data')
	357
	358	mosi_bit, miso_bit = 0, 0
	359	if self.miso is not None:
	360	if len(self.mosi) < 0:
	361	raise Exception('No available data')
	362	miso_bit = self.miso.pop(0)
	363	if self.miso is not None:
	364	if len(self.miso) < 0:
	365	raise Exception('No available data')
	366	mosi_bit = self.mosi.pop(0)
	367
	368	if channel == Channel.MOSI:
	369	return mosi_bit
	370	return miso_bit
	371
	372	def decode(self, ss, es, data):
	373	ptype = data[0]
	374
	375	if ptype == 'CS-CHANGE':
	376	cs_old, cs_new = data[1:]
	377	if cs_old is not None and cs_old == 1 and cs_new == 0:
88098c75	378	self.ss, self.es = ss, es
f47d3a2d TP	379	self.state = 'ADDRESS-BYTE'
	380	else:
	381	self.state = 'IDLE'
	382
	383	elif ptype == 'BITS':
	384	if data[1] is not None:
	385	self.mosi = list(reversed(data[1]))
	386	if data[2] is not None:
	387	self.miso = list(reversed(data[2]))
	388
	389	if self.mosi is None and self.miso is None:
	390	return
	391
	392	if self.state == 'ADDRESS-BYTE':
	393	# OPERATION BIT
	394	op_bit = self.get_bit(Channel.MOSI)
88098c75	395	self.put(op_bit[1], op_bit[2], self.out_ann,
7b0f3c78	396	[Ann.READ if op_bit[0] else Ann.WRITE, operations[op_bit[0]]])
88098c75	397	self.operation = Operation.READ if op_bit[0] else Operation.WRITE
f47d3a2d TP	398	# MULTIPLE-BYTE BIT
f47d3a2d TP	399	mb_bit = self.get_bit(Channel.MOSI)
7b0f3c78	400	self.put(mb_bit[1], mb_bit[2], self.out_ann, [Ann.MB, number_bytes[mb_bit[0]]])
f47d3a2d TP	401
	402	# REGISTER 6-BIT ADDRESS
	403	self.address = 0
	404	start_sample = self.mosi[0][1]
	405	addr_bit = []
	406	for i in range(6):
	407	addr_bit = self.get_bit(Channel.MOSI)
	408	self.address \|= addr_bit[0]
	409	self.address <<= 1
	410	self.address >>= 1
	411	self.put(start_sample, addr_bit[2], self.out_ann,
7b0f3c78	412	[Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X'
f47d3a2d TP	413	% self.address, '0x%02X' % self.address]])
	414	self.ss = -1
	415	self.state = 'DATA'
	416
	417	elif self.state == 'DATA':
88098c75	418	self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)
f47d3a2d	419
88098c75	420	self.mosi, self.miso = [], []
f47d3a2d	421	if self.ss == -1:
88098c75	422	self.ss, self.es = self.reg[0][1], es
f47d3a2d TP	423	self.samples_per_bit = self.reg[0][2] - self.ss
	424
	425	if len(self.reg) < 8:
	426	return
	427	else:
	428	reg_value = 0
	429	reg_bit = []
	430	for offset in range(7, -1, -1):
	431	reg_bit = self.reg.pop(0)
	432
	433	mask = reg_bit[0] << offset
	434	reg_value \|= mask
	435
	436	if self.address < 0x00 or self.address > 0x39:
	437	return
	438
	439	if self.address in [0x32, 0x34, 0x36]:
	440	self.start_index = self.ss
	441
	442	if 0x1D > self.address >= 0x00:
7b0f3c78 UH	443	self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, [str(self.address)]])
7b0f3c78 UH	444	self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]])
f47d3a2d	445	else:
7b0f3c78	446	self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]])
f47d3a2d TP	447	handle_reg = getattr(self, 'handle_reg_0x%02X' % self.address)
	448	handle_reg(reg_value)
	449
	450	self.reg = []
	451	self.address += 1
	452	self.ss = -1