}
if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
return ret;
if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
}
if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
return ret;
if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {