SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
- SR_CONF_NUM_TIMEBASE | SR_CONF_GET,
+ SR_CONF_NUM_HDIV | SR_CONF_GET,
SR_CONF_SAMPLERATE | SR_CONF_GET,
+ SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
static const uint32_t analog_devopts[] = {
SR_CONF_NUM_VDIV | SR_CONF_GET,
SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
- SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
static const uint64_t timebases[][2] = {
DS2000,
DS2000A,
DSO1000,
+ DS1000Z,
};
/* short name, full name */
[DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
{50, 1}, {2, 1000}, 12, 600, 1048576},
[DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
- {500, 1}, {2, 1000}, 14, 1400, 14000},
+ {500, 1}, {500, 1000000}, 14, 1400, 14000},
[DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
{1000, 1}, {500, 1000000}, 14, 1400, 14000},
[DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
{50, 1}, {2, 1000}, 12, 600, 20480},
+ [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
+ {50, 1}, {1, 1000}, 12, 1200, 12000000},
};
#define SERIES(x) &supported_series[x]
{SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
{SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
{SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
+ {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, 4, false},
+ {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, 4, false},
+ {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false},
+ {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false},
+ {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false},
+ {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true},
+ {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true},
+ {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true},
+ {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, 4, true},
};
SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
g_free(devc->trigger_source);
g_free(devc->trigger_slope);
g_free(devc->analog_groups);
- g_free(devc->digital_group);
g_free(devc);
}
for (i = 0; i < model->analog_channels; i++) {
if (!(channel_name = g_strdup_printf("CH%d", i + 1)))
return NULL;
- ch = sr_channel_new(i, SR_CHANNEL_ANALOG, TRUE, channel_name);
- sdi->channels = g_slist_append(sdi->channels, ch);
+ ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
}
if (devc->model->has_digital) {
- devc->digital_group = g_malloc0(sizeof(struct sr_channel_group*));
+ devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
if (!(channel_name = g_strdup_printf("D%d", i)))
return NULL;
- ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, channel_name);
+ ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
g_free(channel_name);
- sdi->channels = g_slist_append(sdi->channels, ch);
devc->digital_group->channels = g_slist_append(
devc->digital_group->channels, ch);
}
}
for (i = 0; i < NUM_VDIV; i++)
- if (!memcmp(&devc->model->series->min_vdiv, &vdivs[i], sizeof(uint64_t[2])))
+ if (!memcmp(&devc->model->series->min_vdiv, &vdivs[i], sizeof(uint64_t[2]))) {
devc->vdivs = &vdivs[i];
+ devc->num_vdivs = NUM_VDIV - i;
+ }
if (!(devc->buffer = g_try_malloc(ACQ_BUFFER_SIZE)))
return NULL;
const char *tmp_str;
uint64_t samplerate;
int analog_channel = -1;
- float smallest_diff = 0.0000000001;
+ float smallest_diff = INFINITY;
int idx = -1;
unsigned i;
}
switch (key) {
- case SR_CONF_NUM_TIMEBASE:
+ case SR_CONF_NUM_HDIV:
*data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
break;
case SR_CONF_NUM_VDIV:
- *data = g_variant_new_int32(NUM_VDIV);
+ *data = g_variant_new_int32(devc->num_vdivs);
+ break;
case SR_CONF_DATA_SOURCE:
if (devc->data_source == DATA_SOURCE_LIVE)
*data = g_variant_new_string("Live");
return SR_ERR_ARG;
/* If a channel group is specified, it must be a valid one. */
- if (cg) {
- for (i = 0; i < devc->model->analog_channels; i++)
- if (cg == devc->analog_groups[i])
- break;
- if (i >= devc->model->analog_channels) {
- sr_err("Invalid channel group specified.");
- return SR_ERR;
- }
+ if (cg && !g_slist_find(sdi->channel_groups, cg)) {
+ sr_err("Invalid channel group specified.");
+ return SR_ERR;
}
switch (key) {
return SR_ERR_CHANNEL_GROUP;
}
g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
- for (i = 0; i < NUM_VDIV; i++) {
+ for (i = 0; i < devc->num_vdivs; i++) {
rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
tuple = g_variant_new_tuple(rational, 2);
struct dev_context *devc;
struct sr_channel *ch;
struct sr_datafeed_packet packet;
+ gboolean some_digital;
GSList *l;
if (sdi->status != SR_ST_ACTIVE)
devc->num_frames = 0;
+ some_digital = FALSE;
for (l = sdi->channels; l; l = l->next) {
ch = l->data;
sr_dbg("handling channel %s", ch->name);
if (ch->type == SR_CHANNEL_ANALOG) {
if (ch->enabled)
- devc->enabled_analog_channels = g_slist_append(
- devc->enabled_analog_channels, ch);
+ devc->enabled_channels = g_slist_append(
+ devc->enabled_channels, ch);
if (ch->enabled != devc->analog_channels[ch->index]) {
/* Enabled channel is currently disabled, or vice versa. */
if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
devc->analog_channels[ch->index] = ch->enabled;
}
} else if (ch->type == SR_CHANNEL_LOGIC) {
+ /* Only one list entry for DS1000D series. All channels are retrieved
+ * together when this entry is processed. */
+ if (ch->enabled && (
+ devc->model->series->protocol > PROTOCOL_V2 ||
+ !some_digital))
+ devc->enabled_channels = g_slist_append(
+ devc->enabled_channels, ch);
if (ch->enabled) {
- devc->enabled_digital_channels = g_slist_append(
- devc->enabled_digital_channels, ch);
+ some_digital = TRUE;
/* Turn on LA module if currently off. */
if (!devc->la_enabled) {
- if (rigol_ds_config_set(sdi, ":LA:DISP ON") != SR_OK)
+ if (rigol_ds_config_set(sdi,
+ devc->model->series->protocol >= PROTOCOL_V4 ?
+ ":LA:STAT ON" : ":LA:DISP ON") != SR_OK)
return SR_ERR;
devc->la_enabled = TRUE;
}
}
if (ch->enabled != devc->digital_channels[ch->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (rigol_ds_config_set(sdi, ":DIG%d:TURN %s", ch->index,
+ if (rigol_ds_config_set(sdi,
+ devc->model->series->protocol >= PROTOCOL_V4 ?
+ ":LA:DIG%d:DISP %s" : ":DIG%d:TURN %s", ch->index,
ch->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
devc->digital_channels[ch->index] = ch->enabled;
}
}
- if (!devc->enabled_analog_channels && !devc->enabled_digital_channels)
+ if (!devc->enabled_channels)
return SR_ERR;
/* Turn off LA module if on and no digital channels selected. */
- if (devc->la_enabled && !devc->enabled_digital_channels)
- if (rigol_ds_config_set(sdi, ":LA:DISP OFF") != SR_OK)
+ if (devc->la_enabled && !some_digital)
+ if (rigol_ds_config_set(sdi,
+ devc->model->series->protocol >= PROTOCOL_V4 ?
+ ":LA:STAT OFF" : ":LA:DISP OFF") != SR_OK)
return SR_ERR;
/* Set memory mode. */
/* Send header packet to the session bus. */
std_session_send_df_header(cb_data, LOG_PREFIX);
- if (devc->enabled_analog_channels)
- devc->channel_entry = devc->enabled_analog_channels;
- else
- devc->channel_entry = devc->enabled_digital_channels;
+ devc->channel_entry = devc->enabled_channels;
if (rigol_ds_capture_start(sdi) != SR_OK)
return SR_ERR;
packet.type = SR_DF_END;
sr_session_send(sdi, &packet);
- g_slist_free(devc->enabled_analog_channels);
- g_slist_free(devc->enabled_digital_channels);
- devc->enabled_analog_channels = NULL;
- devc->enabled_digital_channels = NULL;
+ g_slist_free(devc->enabled_channels);
+ devc->enabled_channels = NULL;
scpi = sdi->conn;
sr_scpi_source_remove(sdi->session, scpi);
projects / libsigrok.git / blobdiff