rigol-dg: Initial Rigol DG1000z driver implementation.

[libsigrok.git] / src / hardware / rigol-dg / protocol.h

diff --git a/src/hardware/rigol-dg/protocol.h b/src/hardware/rigol-dg/protocol.h
index db8b463ace6aa5101070c16cf7a18f69dbe6fd46..bff7c2089e339dde067d5a51b0331f27f57e2289 100644 (file)
--- a/src/hardware/rigol-dg/protocol.h
+++ b/src/hardware/rigol-dg/protocol.h
@@ -27,9 +27,101 @@
 
 #define LOG_PREFIX "rigol-dg"
 
+enum psg_commands {
+       PSG_CMD_SETUP_REMOTE,
+       PSG_CMD_SETUP_LOCAL,
+       PSG_CMD_SELECT_CHANNEL,
+       PSG_CMD_GET_CHANNEL,
+       PSG_CMD_GET_ENABLED,
+       PSG_CMD_SET_ENABLE,
+       PSG_CMD_SET_DISABLE,
+       PSG_CMD_GET_SOURCE,
+       PSG_CMD_SET_SOURCE,
+       PSG_CMD_SET_FREQUENCY,
+       PSG_CMD_GET_FREQUENCY,
+       PSG_CMD_SET_AMPLITUDE,
+       PSG_CMD_GET_AMPLITUDE,
+       PSG_CMD_GET_OFFSET,
+       PSG_CMD_SET_OFFSET,
+       PSG_CMD_GET_PHASE,
+       PSG_CMD_SET_PHASE,
+       PSG_CMD_GET_DCYCL_PULSE,
+       PSG_CMD_SET_DCYCL_PULSE,
+       PSG_CMD_GET_DCYCL_SQUARE,
+       PSG_CMD_SET_DCYCL_SQUARE,
+       PSG_CMD_COUNTER_GET_ENABLED,
+       PSG_CMD_COUNTER_SET_ENABLE,
+       PSG_CMD_COUNTER_SET_DISABLE,
+       PSG_CMD_COUNTER_MEASURE,
+};
+
+enum waveform_type {
+       WF_DC = 0,
+       WF_SINE,
+       WF_SQUARE,
+       WF_RAMP,
+       WF_PULSE,
+       WF_NOISE,
+       WF_ARB,
+};
+
+enum waveform_options {
+       WFO_FREQUENCY = 1,
+       WFO_AMPLITUDE = 2,
+       WFO_OFFSET = 4,
+       WFO_PHASE = 8,
+       WFO_DUTY_CYCLE = 16,
+};
+
+struct waveform_spec {
+       const char *name;
+       enum waveform_type waveform;
+       double freq_min;
+       double freq_max;
+       double freq_step;
+       uint32_t opts;
+};
+
+struct channel_spec {
+       const char *name;
+       const struct waveform_spec *waveforms;
+       uint32_t num_waveforms;
+};
+
+struct channel_status {
+       enum waveform_type wf;
+       const struct waveform_spec *wf_spec;
+       double freq;
+       double ampl;
+       double offset;
+       double phase;
+};
+
+struct device_spec {
+       const char *vendor;
+       const char *model;
+       const uint32_t *devopts;
+       const uint32_t num_devopts;
+       const uint32_t *devopts_cg;
+       const uint32_t num_devopts_cg;
+       const struct channel_spec *channels;
+       const uint32_t num_channels;
+       const struct scpi_command *cmdset;
+};
+
 struct dev_context {
+       const struct scpi_command *cmdset;
+       const struct device_spec *device;
+       struct channel_status *ch_status;
+       struct sr_sw_limits limits;
+       gboolean counter_enabled;
 };
 
+SR_PRIV const char *rigol_dg_waveform_to_string(enum waveform_type type);
+SR_PRIV const struct waveform_spec *rigol_dg_get_waveform_spec(
+               const struct channel_spec *ch, enum waveform_type wf);
+SR_PRIV int rigol_dg_get_channel_state(const struct sr_dev_inst *sdi,
+               const struct sr_channel_group *cg);
 SR_PRIV int rigol_dg_receive_data(int fd, int revents, void *cb_data);
 
 #endif