#define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
/*
- * List of supported devices and their features. See @ref kingst_model
+ * List of known devices and their features. See @ref kingst_model
* for the fields' type and meaning. Table is sorted by EEPROM magic.
+ * More specific items need to go first (additional byte[2/6]). Not
+ * all devices are covered by this driver implementation, but telling
+ * users what was detected is considered useful.
*
- * TODO
- * - Below LA1016 properties were guessed, need verification.
- * - Add LA5016 and LA5032 devices when their EEPROM magic is known.
- * - Does LA1010 fit the driver implementation? Samplerates vary with
- * channel counts, lack of local sample memory. Most probably not.
+ * TODO Verify the identification of models that were not tested before.
*/
static const struct kingst_model models[] = {
- { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, },
- { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, },
- { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, },
- { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, },
+ { 0x02, 0x01, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+ { 0x02, 0x00, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, },
+ { 0x03, 0x01, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+ { 0x03, 0x00, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, },
+ { 0x04, 0x00, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x05, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x06, 0x00, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), },
+ { 0x07, 0x00, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x08, 0x00, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+ { 0x09, 0x00, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+ { 0x0a, 0x00, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x41, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
};
/* USB vendor class control requests, executed by the Cypress FX2 MCU. */
static int set_sample_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
+ uint64_t baseclock;
uint64_t min_samplerate, eff_samplerate;
uint64_t stream_bandwidth;
uint16_t divider_u16;
devc = sdi->priv;
+ /*
+ * The base clock need not be identical to the maximum samplerate,
+ * and differs between models. The 500MHz devices even use a base
+ * clock of 800MHz, and communicate divider 1 to the hardware to
+ * configure the 500MHz samplerate. This allows them to operate at
+ * a 200MHz samplerate which uses divider 4.
+ */
if (devc->samplerate > devc->model->samplerate) {
sr_err("Too high a sample rate: %" PRIu64 ".",
devc->samplerate);
return SR_ERR_ARG;
}
- min_samplerate = devc->model->samplerate;
+ baseclock = devc->model->baseclock;
+ if (!baseclock)
+ baseclock = devc->model->samplerate;
+ min_samplerate = baseclock;
min_samplerate /= 65536;
if (devc->samplerate < min_samplerate) {
sr_err("Too low a sample rate: %" PRIu64 ".",
devc->samplerate);
return SR_ERR_ARG;
}
- divider_u16 = devc->model->samplerate / devc->samplerate;
- eff_samplerate = devc->model->samplerate / divider_u16;
+ divider_u16 = baseclock / devc->samplerate;
+ eff_samplerate = baseclock / divider_u16;
+ if (eff_samplerate > devc->model->samplerate)
+ eff_samplerate = devc->model->samplerate;
ret = sr_sw_limits_get_remain(&devc->sw_limits,
&limit_samples, NULL, NULL, NULL);
const uint8_t *rdptr;
uint8_t date_yy, date_mm;
uint8_t dinv_yy, dinv_mm;
- uint8_t magic;
+ uint8_t magic, magic2;
size_t model_idx;
const struct kingst_model *model;
int ret;
sr_spew("EEPROM magic bytes %s.", txt->str);
sr_hexdump_free(txt);
}
- if ((buf[0] ^ buf[1]) == 0xff) {
- /* Primary copy of magic passes complement check. */
+ magic = 0;
+ magic2 = 0;
+ if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) {
+ /* Primary copy of magic passes complement check (4 bytes). */
+ magic = buf[0];
+ magic2 = buf[2];
+ sr_dbg("Using primary magic 0x%hhx (0x%hhx).", magic, magic2);
+ } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) {
+ /* Backup copy of magic passes complement check (4 bytes). */
+ magic = buf[4];
+ magic2 = buf[6];
+ sr_dbg("Using secondary magic 0x%hhx (0x%hhx).", magic, magic2);
+ } else if ((buf[0] ^ buf[1]) == 0xff) {
+ /* Primary copy of magic passes complement check (2 bytes). */
magic = buf[0];
- sr_dbg("Using primary magic, value %d.", (int)magic);
+ sr_dbg("Using primary magic 0x%hhx.", magic);
} else if ((buf[4] ^ buf[5]) == 0xff) {
- /* Backup copy of magic passes complement check. */
+ /* Backup copy of magic passes complement check (2 bytes). */
magic = buf[4];
- sr_dbg("Using backup magic, value %d.", (int)magic);
+ sr_dbg("Using secondary magic 0x%hhx.", magic);
} else {
sr_err("Cannot find consistent device type identification.");
- magic = 0;
}
devc->identify_magic = magic;
+ devc->identify_magic2 = magic2;
devc->model = NULL;
for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
model = &models[model_idx];
if (model->magic != magic)
continue;
+ if (model->magic2 && model->magic2 != magic2)
+ continue;
devc->model = model;
sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
model->name, model->channel_count,
devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
model->fpga_stem);
sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
+ if (!model->channel_count) {
+ sr_warn("Device lacks logic channels. Not supported.");
+ devc->model = NULL;
+ }
break;
}
if (!devc->model) {
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