/*
* This file is part of the libsigrok project.
*
+ * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
* Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
* Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
return SR_OK;
}
+/* HACK Experiment to spot FPGA registers of interest. */
+static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
+ const char *caption, size_t reg_lower, size_t reg_upper)
+{
+ static const size_t dump_chunk_len = 16;
+
+ size_t rdlen;
+ uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */
+ const uint8_t *rdptr;
+ int ret;
+ size_t dump_addr, indent, dump_len;
+ GString *txt;
+
+ if (sr_log_loglevel_get() < SR_LOG_SPEW)
+ return;
+
+ if (!reg_lower && !reg_upper) {
+ reg_lower = 0;
+ reg_upper = sizeof(rdbuf);
+ }
+ if (reg_upper - reg_lower > sizeof(rdbuf))
+ reg_upper = sizeof(rdbuf) - reg_lower;
+
+ rdlen = reg_upper - reg_lower;
+ ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
+ if (ret != SR_OK) {
+ sr_err("Cannot get registers space.");
+ return;
+ }
+ rdptr = rdbuf;
+
+ sr_spew("FPGA registers dump: %s", caption ? : "for fun");
+ dump_addr = reg_lower;
+ while (rdlen) {
+ dump_len = rdlen;
+ indent = dump_addr % dump_chunk_len;
+ if (dump_len > dump_chunk_len)
+ dump_len = dump_chunk_len;
+ if (dump_len + indent > dump_chunk_len)
+ dump_len = dump_chunk_len - indent;
+ txt = sr_hexdump_new(rdptr, dump_len);
+ sr_spew(" %04zx %*s%s",
+ dump_addr, (int)(3 * indent), "", txt->str);
+ sr_hexdump_free(txt);
+ dump_addr += dump_len;
+ rdptr += dump_len;
+ rdlen -= dump_len;
+ }
+}
+
/*
* Check the necessity for FPGA bitstream upload, because another upload
* would take some 600ms which is undesirable after program startup. Try
const uint8_t *rdptr;
sr_dbg("Checking operation of the FPGA bitstream.");
+ la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
init_rsp = ~0;
ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
}
SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
- struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
+ struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload)
{
struct dev_context *devc;
- char *fw_file;
+ uint16_t pid;
+ char *fw;
int ret;
devc = sdi ? sdi->priv : NULL;
+ if (!devc || !devc->usb_pid)
+ return SR_ERR_ARG;
+ pid = devc->usb_pid;
- fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id);
- sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file);
+ fw = g_strdup_printf(MCU_FWFILE_FMT, pid);
+ sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw);
+ devc->mcu_firmware = g_strdup(fw);
- ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
- if (ret != SR_OK) {
- g_free(fw_file);
+ if (skip_upload)
+ ret = SR_OK;
+ else
+ ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw);
+ g_free(fw);
+ if (ret != SR_OK)
return ret;
- }
-
- if (devc) {
- devc->mcu_firmware = fw_file;
- fw_file = NULL;
- }
- g_free(fw_file);
return SR_OK;
}
devc->trigger_marked = FALSE;
devc->total_samples = 0;
+ la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
+
/* Initiate the download of acquired sample data. */
std_session_send_df_frame_begin(sdi);
devc->frame_begin_sent = TRUE;
}
state = run_state(sdi);
- if (state != 0x85e9) {
- sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state);
+ if ((state & 0xfff0) != 0x85e0) {
+ sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state);
}
ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);