/*
* This file is part of the libsigrok project.
*
+ * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
* Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
* Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
-#define REG_TRIGGER 0x20 /* write level and edge trigger config. */
+#define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
+#define REG_UNKNOWN_30 0x30
#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
#define REG_PWM1 0x70 /* Write config for user PWM1. */
#define REG_PWM2 0x78 /* Write config for user PWM2. */
+/* Bit patterns to write to REG_CAPT_MODE. */
+#define CAPTMODE_TO_RAM 0x00
+#define CAPTMODE_STREAM 0x01
+
/* Bit patterns to write to REG_RUN, setup run mode. */
#define RUNMODE_HALT 0x00
#define RUNMODE_RUN 0x03
libusb_error_name(ret));
sr_err("Cannot read %d bytes from USB: %s.",
wLength, libusb_error_name(ret));
- return SR_ERR;
+ return SR_ERR_IO;
}
return SR_OK;
libusb_error_name(ret));
sr_err("Cannot write %d bytes to USB: %s.",
wLength, libusb_error_name(ret));
- return SR_ERR;
+ return SR_ERR_IO;
}
return SR_OK;
}
+/* HACK Experiment to spot FPGA registers of interest. */
+static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
+ const char *caption, size_t reg_lower, size_t reg_upper)
+{
+ static const size_t dump_chunk_len = 16;
+
+ size_t rdlen;
+ uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */
+ const uint8_t *rdptr;
+ int ret;
+ size_t dump_addr, indent, dump_len;
+ GString *txt;
+
+ if (sr_log_loglevel_get() < SR_LOG_SPEW)
+ return;
+
+ if (!reg_lower && !reg_upper) {
+ reg_lower = 0;
+ reg_upper = sizeof(rdbuf);
+ }
+ if (reg_upper - reg_lower > sizeof(rdbuf))
+ reg_upper = sizeof(rdbuf) - reg_lower;
+
+ rdlen = reg_upper - reg_lower;
+ ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
+ if (ret != SR_OK) {
+ sr_err("Cannot get registers space.");
+ return;
+ }
+ rdptr = rdbuf;
+
+ sr_spew("FPGA registers dump: %s", caption ? : "for fun");
+ dump_addr = reg_lower;
+ while (rdlen) {
+ dump_len = rdlen;
+ indent = dump_addr % dump_chunk_len;
+ if (dump_len > dump_chunk_len)
+ dump_len = dump_chunk_len;
+ if (dump_len + indent > dump_chunk_len)
+ dump_len = dump_chunk_len - indent;
+ txt = sr_hexdump_new(rdptr, dump_len);
+ sr_spew(" %04zx %*s%s",
+ dump_addr, (int)(3 * indent), "", txt->str);
+ sr_hexdump_free(txt);
+ dump_addr += dump_len;
+ rdptr += dump_len;
+ rdlen -= dump_len;
+ }
+}
+
/*
* Check the necessity for FPGA bitstream upload, because another upload
* would take some 600ms which is undesirable after program startup. Try
static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
{
uint8_t init_rsp;
+ uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
int ret;
uint16_t run_state;
uint8_t pwm_en;
size_t read_len;
- uint8_t buff[sizeof(run_state)];
const uint8_t *rdptr;
sr_dbg("Checking operation of the FPGA bitstream.");
+ la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
init_rsp = ~0;
ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
if (len < 0) {
sr_err("Cannot read FPGA bitstream.");
sr_resource_close(drvc->sr_ctx, &bitstream);
- return SR_ERR;
+ return SR_ERR_IO;
}
} else {
/* Zero-pad until 'zero_pad_to'. */
if (ret != 0) {
sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.",
pos, (int)len, libusb_error_name(ret));
- ret = SR_ERR;
+ ret = SR_ERR_IO;
break;
}
if (act_len != len) {
sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.",
pos, (int)len, act_len);
- ret = SR_ERR;
+ ret = SR_ERR_IO;
break;
}
pos += len;
if (resp != 0) {
sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
resp);
- return SR_ERR;
+ return SR_ERR_DATA;
}
g_usleep(30 * 1000);
static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
{
- struct dev_context *devc;
int ret;
uint16_t duty_R79, duty_R56;
- uint8_t buf[2 * sizeof(uint16_t)];
+ uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
uint8_t *wrptr;
- devc = sdi->priv;
-
/* Clamp threshold setting to valid range for LA2016. */
- if (voltage > 4.0) {
- voltage = 4.0;
- } else if (voltage < -4.0) {
- voltage = -4.0;
+ if (voltage > LA2016_THR_VOLTAGE_MAX) {
+ voltage = LA2016_THR_VOLTAGE_MAX;
+ } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
+ voltage = -LA2016_THR_VOLTAGE_MAX;
}
/*
sr_err("Cannot set threshold voltage %.2fV.", voltage);
return ret;
}
- devc->threshold_voltage = voltage;
return SR_OK;
}
-static int enable_pwm(const struct sr_dev_inst *sdi, gboolean p1, gboolean p2)
-{
- struct dev_context *devc;
- uint8_t cfg;
- int ret;
-
- devc = sdi->priv;
-
- cfg = 0;
- if (p1)
- cfg |= 1U << 0;
- if (p2)
- cfg |= 1U << 1;
- sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg);
-
- ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg));
- if (ret != SR_OK) {
- sr_err("Cannot setup PWM enabled state.");
- return ret;
- }
-
- devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
- devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
-
- return SR_OK;
-}
-
-static int configure_pwm(const struct sr_dev_inst *sdi, uint8_t which,
- float freq, float duty)
+/*
+ * Communicates a channel's configuration to the device after the
+ * parameters may have changed. Configuration of one channel may
+ * interfere with other channels since they share FPGA registers.
+ */
+static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
{
- static uint8_t ctrl_reg_tab[] = { REG_PWM1, REG_PWM2, };
+ static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
struct dev_context *devc;
- uint8_t ctrl_reg;
- struct pwm_setting_dev cfg;
- struct pwm_setting *setting;
+ struct pwm_setting *params;
+ uint8_t reg_base;
+ double val_f;
+ uint32_t val_u;
+ uint32_t period, duty;
+ size_t ch;
int ret;
- uint8_t buf[2 * sizeof(uint32_t)];
+ uint8_t enable_all, enable_cfg, reg_val;
+ uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
uint8_t *wrptr;
devc = sdi->priv;
+ if (idx >= ARRAY_SIZE(devc->pwm_setting))
+ return SR_ERR_ARG;
+ params = &devc->pwm_setting[idx];
+ if (idx >= ARRAY_SIZE(reg_bases))
+ return SR_ERR_ARG;
+ reg_base = reg_bases[idx];
- if (which < 1 || which > ARRAY_SIZE(ctrl_reg_tab)) {
- sr_err("Invalid PWM channel: %d.", which);
- return SR_ERR;
- }
- if (freq < 0 || freq > MAX_PWM_FREQ) {
- sr_err("Too high a PWM frequency: %.1f.", freq);
- return SR_ERR;
- }
- if (duty < 0 || duty > 100) {
- sr_err("Invalid PWM duty cycle: %f.", duty);
- return SR_ERR;
+ /*
+ * Map application's specs to hardware register values. Do math
+ * in floating point initially, but convert to u32 eventually.
+ */
+ sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
+ idx, params->enabled ? 1 : 0, params->freq, params->duty);
+ val_f = PWM_CLOCK;
+ val_f /= params->freq;
+ val_u = val_f;
+ period = val_u;
+ val_f = period;
+ val_f *= params->duty;
+ val_f /= 100.0;
+ val_f += 0.5;
+ val_u = val_f;
+ duty = val_u;
+ sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
+ (unsigned)reg_base, (unsigned)period, (unsigned)duty);
+
+ /* Get the "enabled" state of all supported PWM channels. */
+ enable_all = 0;
+ for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
+ if (!devc->pwm_setting[ch].enabled)
+ continue;
+ enable_all |= 1U << ch;
}
+ enable_cfg = 1U << idx;
+ sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
+ enable_all, enable_cfg);
- memset(&cfg, 0, sizeof(cfg));
- cfg.period = (uint32_t)(PWM_CLOCK / freq);
- cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
- sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty);
-
- ctrl_reg = ctrl_reg_tab[which - 1];
- wrptr = buf;
- write_u32le_inc(&wrptr, cfg.period);
- write_u32le_inc(&wrptr, cfg.duty);
- ret = ctrl_out(sdi, CMD_FPGA_SPI, ctrl_reg, 0, buf, wrptr - buf);
+ /*
+ * Disable the to-get-configured channel before its parameters
+ * will change. Or disable and exit when the channel is supposed
+ * to get turned off.
+ */
+ sr_spew("PWM config, disabling before param change.");
+ reg_val = enable_all & ~enable_cfg;
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
+ ®_val, sizeof(reg_val));
if (ret != SR_OK) {
- sr_err("Cannot setup PWM%d configuration %d %d.",
- which, cfg.period, cfg.duty);
+ sr_err("Cannot adjust PWM enabled state.");
return ret;
}
+ if (!params->enabled)
+ return SR_OK;
- setting = &devc->pwm_setting[which - 1];
- setting->freq = freq;
- setting->duty = duty;
-
- return SR_OK;
-}
-
-static int set_defaults(const struct sr_dev_inst *sdi)
-{
- struct dev_context *devc;
- int ret;
-
- devc = sdi->priv;
-
- ret = set_threshold_voltage(sdi, devc->threshold_voltage);
- if (ret)
- return ret;
-
- ret = enable_pwm(sdi, FALSE, FALSE);
- if (ret)
- return ret;
-
- ret = configure_pwm(sdi, 1, SR_KHZ(1), 50);
- if (ret)
- return ret;
-
- ret = configure_pwm(sdi, 2, SR_KHZ(100), 50);
- if (ret)
+ /* Write register values to device. */
+ sr_spew("PWM config, sending new parameters.");
+ wrptr = buf;
+ write_u32le_inc(&wrptr, period);
+ write_u32le_inc(&wrptr, duty);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
+ if (ret != SR_OK) {
+ sr_err("Cannot change PWM parameters.");
return ret;
+ }
- ret = enable_pwm(sdi, TRUE, TRUE);
- if (ret)
+ /* Enable configured channel after write completion. */
+ sr_spew("PWM config, enabling after param change.");
+ reg_val = enable_all | enable_cfg;
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
+ ®_val, sizeof(reg_val));
+ if (ret != SR_OK) {
+ sr_err("Cannot adjust PWM enabled state.");
return ret;
+ }
return SR_OK;
}
-static uint16_t get_channels_mask(const struct sr_dev_inst *sdi)
+static uint32_t get_channels_mask(const struct sr_dev_inst *sdi)
{
- uint16_t channels;
+ uint32_t channels;
GSList *l;
struct sr_channel *ch;
{
struct dev_context *devc;
struct sr_trigger *trigger;
- struct trigger_cfg cfg;
+ struct trigger_cfg {
+ uint32_t channels; /* Actually: Enabled channels? */
+ uint32_t enabled; /* Actually: Triggering channels? */
+ uint32_t level;
+ uint32_t high_or_falling;
+ } cfg;
GSList *stages;
GSList *channel;
struct sr_trigger_stage *stage1;
struct sr_trigger_match *match;
- uint16_t ch_mask;
+ uint32_t ch_mask;
int ret;
- uint8_t buf[4 * sizeof(uint32_t)];
+ uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
uint8_t *wrptr;
devc = sdi->priv;
stage1 = stages->data;
if (stages->next) {
sr_err("Only one trigger stage supported for now.");
- return SR_ERR;
+ return SR_ERR_ARG;
}
channel = stage1->matches;
while (channel) {
case SR_TRIGGER_RISING:
if ((cfg.enabled & ~cfg.level)) {
sr_err("Device only supports one edge trigger.");
- return SR_ERR;
+ return SR_ERR_ARG;
}
cfg.level &= ~ch_mask;
cfg.high_or_falling &= ~ch_mask;
case SR_TRIGGER_FALLING:
if ((cfg.enabled & ~cfg.level)) {
sr_err("Device only supports one edge trigger.");
- return SR_ERR;
+ return SR_ERR_ARG;
}
cfg.level &= ~ch_mask;
cfg.high_or_falling |= ch_mask;
break;
default:
sr_err("Unknown trigger condition.");
- return SR_ERR;
+ return SR_ERR_ARG;
}
cfg.enabled |= ch_mask;
channel = channel->next;
}
}
sr_dbg("Set trigger config: "
- "channels 0x%04x, trigger-enabled 0x%04x, "
+ "enabled-channels 0x%04x, triggering-channels 0x%04x, "
"level-triggered 0x%04x, high/falling 0x%04x.",
cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
devc = sdi->priv;
- if (devc->cur_samplerate > devc->model->samplerate) {
+ if (devc->samplerate > devc->model->samplerate) {
sr_err("Too high a sample rate: %" PRIu64 ".",
- devc->cur_samplerate);
+ devc->samplerate);
return SR_ERR_ARG;
}
min_samplerate = devc->model->samplerate;
min_samplerate /= 65536;
- if (devc->cur_samplerate < min_samplerate) {
+ if (devc->samplerate < min_samplerate) {
sr_err("Too low a sample rate: %" PRIu64 ".",
- devc->cur_samplerate);
+ devc->samplerate);
return SR_ERR_ARG;
}
- divider_u16 = devc->model->samplerate / devc->cur_samplerate;
+ divider_u16 = devc->model->samplerate / devc->samplerate;
eff_samplerate = devc->model->samplerate / divider_u16;
ret = sr_sw_limits_get_remain(&devc->sw_limits,
int ret;
uint16_t state;
- uint8_t buff[sizeof(state)];
+ uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
const uint8_t *rdptr;
const char *label;
{
struct dev_context *devc;
int ret;
- uint8_t buf[3 * sizeof(uint32_t)];
+ uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
const uint8_t *rdptr;
devc = sdi->priv;
devc->info.n_rep_packets_before_trigger,
devc->info.write_pos, devc->info.write_pos);
- if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) {
- sr_warn("Unexpected packets count %lu, not a multiple of %d.",
+ if (devc->info.n_rep_packets % devc->packets_per_chunk) {
+ sr_warn("Unexpected packets count %lu, not a multiple of %lu.",
(unsigned long)devc->info.n_rep_packets,
- NUM_PACKETS_IN_CHUNK);
+ (unsigned long)devc->packets_per_chunk);
}
return SR_OK;
}
SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
- struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
+ struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload)
{
struct dev_context *devc;
- char *fw_file;
+ uint16_t pid;
+ char *fw;
int ret;
devc = sdi ? sdi->priv : NULL;
+ if (!devc || !devc->usb_pid)
+ return SR_ERR_ARG;
+ pid = devc->usb_pid;
- fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id);
- sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file);
+ fw = g_strdup_printf(MCU_FWFILE_FMT, pid);
+ sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw);
+ devc->mcu_firmware = g_strdup(fw);
- ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
- if (ret != SR_OK) {
- g_free(fw_file);
+ if (skip_upload)
+ ret = SR_OK;
+ else
+ ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw);
+ g_free(fw);
+ if (ret != SR_OK)
return ret;
- }
-
- if (devc) {
- devc->mcu_firmware = fw_file;
- fw_file = NULL;
- }
- g_free(fw_file);
return SR_OK;
}
-SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
+SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
+ double voltage)
{
- struct dev_context *devc;
int ret;
uint8_t cmd;
- devc = sdi->priv;
-
- ret = set_threshold_voltage(sdi, devc->threshold_voltage);
+ ret = set_threshold_voltage(sdi, voltage);
if (ret != SR_OK)
return ret;
- cmd = 0;
+ cmd = CAPTMODE_TO_RAM;
ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
if (ret != SR_OK) {
sr_err("Cannot send command to stop sampling.");
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
int ret;
- uint8_t wrbuf[2 * sizeof(uint32_t)];
+ uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
uint8_t *wrptr;
uint32_t to_read;
uint8_t *buffer;
if (ret != SR_OK)
return ret;
- devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
- devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
+ devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
+ devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
+ devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
+ devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
to_read = devc->n_bytes_to_read;
if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */
to_read = LA2016_USB_BUFSZ;
- else /* One transfer. */
- to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
+ to_read += LA2016_EP6_PKTSZ - 1;
+ to_read /= LA2016_EP6_PKTSZ;
+ to_read *= LA2016_EP6_PKTSZ;
buffer = g_try_malloc(to_read);
if (!buffer) {
sr_dbg("USB bulk transfer size %d bytes.", (int)to_read);
libusb_free_transfer(devc->transfer);
devc->transfer = NULL;
g_free(buffer);
- return SR_ERR;
+ return SR_ERR_IO;
}
return SR_OK;
struct dev_context *devc;
size_t num_pkts;
const uint8_t *rp;
- uint16_t sample_value;
+ uint32_t sample_value;
size_t repetitions;
uint8_t sample_buff[sizeof(sample_value)];
devc->trigger_marked = TRUE;
}
+ sample_value = 0;
rp = packets;
while (num_xfers--) {
- num_pkts = NUM_PACKETS_IN_CHUNK;
+ num_pkts = devc->packets_per_chunk;
while (num_pkts--) {
- sample_value = read_u16le_inc(&rp);
+ /* TODO Verify 32channel layout. */
+ if (devc->model->channel_count == 32)
+ sample_value = read_u32le_inc(&rp);
+ else if (devc->model->channel_count == 16)
+ sample_value = read_u16le_inc(&rp);
repetitions = read_u8_inc(&rp);
devc->total_samples += repetitions;
- write_u16le(sample_buff, sample_value);
+ write_u32le(sample_buff, sample_value);
feed_queue_logic_submit(devc->feed_queue,
sample_buff, repetitions);
sr_sw_limits_update_samples_read(&devc->sw_limits,
devc->trigger_marked = TRUE;
sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
devc->total_samples,
- (double)devc->total_samples / devc->cur_samplerate * 1e3);
+ (double)devc->total_samples / devc->samplerate * 1e3);
}
}
}
*/
if (to_read >= LA2016_USB_BUFSZ)
to_read = LA2016_USB_BUFSZ;
- else
- to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
+ to_read += LA2016_EP6_PKTSZ - 1;
+ to_read /= LA2016_EP6_PKTSZ;
+ to_read *= LA2016_EP6_PKTSZ;
libusb_fill_bulk_transfer(transfer,
usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
transfer->buffer, to_read,
devc->trigger_marked = FALSE;
devc->total_samples = 0;
+ la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
+
/* Initiate the download of acquired sample data. */
std_session_send_df_frame_begin(sdi);
+ devc->frame_begin_sent = TRUE;
ret = la2016_start_download(sdi, receive_transfer);
if (ret != SR_OK) {
sr_err("Cannot start acquisition data download.");
feed_queue_logic_flush(devc->feed_queue);
feed_queue_logic_free(devc->feed_queue);
devc->feed_queue = NULL;
- std_session_send_df_frame_end(sdi);
+ if (devc->frame_begin_sent) {
+ std_session_send_df_frame_end(sdi);
+ devc->frame_begin_sent = FALSE;
+ }
std_session_send_df_end(sdi);
sr_dbg("Download finished, done post processing.");
gboolean show_message)
{
struct dev_context *devc;
- uint8_t buf[8];
+ uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
size_t rdoff, rdlen;
const uint8_t *rdptr;
uint8_t date_yy, date_mm;
}
if (!devc->model) {
sr_err("Cannot identify as one of the supported models.");
- return SR_ERR;
+ return SR_ERR_DATA;
}
return SR_OK;
}
-SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
+SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
const char *bitstream_fn;
}
state = run_state(sdi);
- if (state != 0x85e9) {
- sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state);
+ if ((state & 0xfff0) != 0x85e0) {
+ sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state);
}
- if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot reset USB bulk transfer.");
return ret;
}
sr_dbg("Device should be initialized.");
- ret = set_defaults(sdi);
- if (ret != SR_OK)
- return ret;
-
return SR_OK;
}
-SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
+SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
{
int ret;
- if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot deinitialize device's FPGA.");
return ret;
}
return SR_OK;
}
+
+SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
+{
+ return set_pwm_config(sdi, idx);
+}
projects / libsigrok.git / blobdiff