#include "libsigrok-internal.h"
#include "protocol.h"
-#define UC_FIRMWARE "kingst-la-%04x.fw"
-#define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream"
-#define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream"
-#define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream"
-#define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream"
-
-/* Maximum device capabilities. May differ between models. */
-#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
-#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
-#define MAX_SAMPLE_DEPTH 10e9
-#define MAX_PWM_FREQ SR_MHZ(20)
-#define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */
+/* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
+#define MCU_FWFILE_FMT "kingst-la-%04x.fw"
+#define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
/*
- * Default device configuration. Must be applicable to any of the
- * supported devices (no model specific default values yet). Specific
- * firmware implementation details unfortunately won't let us detect
- * and keep using previously configured values.
- */
-#define LA2016_DFLT_SAMPLERATE SR_MHZ(100)
-#define LA2016_DFLT_SAMPLEDEPTH (5 * 1000 * 1000)
-#define LA2016_DFLT_CAPT_RATIO 5 /* Capture ratio, in percent. */
-
-/* TODO
- * What is the origin and motivation of that 128Mi literal? What is its
- * unit? How does it relate to a device's hardware capabilities? How to
- * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value?
- * It cannot be sample count. Is it memory size in bytes perhaps?
+ * List of supported devices and their features. See @ref kingst_model
+ * for the fields' type and meaning. Table is sorted by EEPROM magic.
+ *
+ * TODO
+ * - Below LA1016 properties were guessed, need verification.
+ * - Add LA5016 and LA5032 devices when their EEPROM magic is known.
+ * - Does LA1010 fit the driver implementation? Samplerates vary with
+ * channel counts, lack of local sample memory. Most probably not.
*/
-#define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024)
+static const struct kingst_model models[] = {
+ { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, },
+ { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, },
+ { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, },
+ { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, },
+};
/* USB vendor class control requests, executed by the Cypress FX2 MCU. */
#define CMD_FPGA_ENABLE 0x10
#define RUNSTATE_TRGD_BIT (1UL << 2)
#define RUNSTATE_POST_BIT (1UL << 3)
+/* Properties related to the layout of capture data downloads. */
+#define NUM_PACKETS_IN_CHUNK 5
+#define TRANSFER_PACKET_LENGTH 16
+
static int ctrl_in(const struct sr_dev_inst *sdi,
uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
void *data, uint16_t wLength)
usb = sdi->conn;
- if ((ret = libusb_control_transfer(usb->devhdl,
- LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
- bRequest, wValue, wIndex, (unsigned char *)data, wLength,
- DEFAULT_TIMEOUT_MS)) != wLength) {
+ ret = libusb_control_transfer(usb->devhdl,
+ LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
+ bRequest, wValue, wIndex, data, wLength,
+ DEFAULT_TIMEOUT_MS);
+ if (ret != wLength) {
sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.",
wLength, bRequest, wValue, wIndex,
libusb_error_name(ret));
usb = sdi->conn;
- if ((ret = libusb_control_transfer(usb->devhdl,
- LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
- bRequest, wValue, wIndex, (unsigned char*)data, wLength,
- DEFAULT_TIMEOUT_MS)) != wLength) {
+ ret = libusb_control_transfer(usb->devhdl,
+ LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
+ bRequest, wValue, wIndex, data, wLength,
+ DEFAULT_TIMEOUT_MS);
+ if (ret != wLength) {
sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.",
wLength, bRequest, wValue, wIndex,
libusb_error_name(ret));
sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
- ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname);
+ ret = sr_resource_open(drvc->sr_ctx, &bitstream,
+ SR_RESOURCE_FIRMWARE, bitstream_fname);
if (ret != SR_OK) {
sr_err("Cannot find FPGA bitstream %s.", bitstream_fname);
return ret;
bitstream_size = (uint32_t)bitstream.size;
wrptr = buffer;
write_u32le_inc(&wrptr, bitstream_size);
- if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer);
+ if (ret != SR_OK) {
sr_err("Cannot initiate FPGA bitstream upload.");
sr_resource_close(drvc->sr_ctx, &bitstream);
return ret;
pos = 0;
while (1) {
if (pos < bitstream.size) {
- len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
+ len = (int)sr_resource_read(drvc->sr_ctx, &bitstream,
+ block, sizeof(block));
if (len < 0) {
sr_err("Cannot read FPGA bitstream.");
sr_resource_close(drvc->sr_ctx, &bitstream);
pos += len;
}
sr_resource_close(drvc->sr_ctx, &bitstream);
- if (ret != 0)
+ if (ret != SR_OK)
return ret;
sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.",
bitstream.size);
static int enable_fpga_bitstream(const struct sr_dev_inst *sdi)
{
int ret;
- uint8_t cmd_resp;
+ uint8_t resp;
- if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
+ ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp));
+ if (ret != SR_OK) {
sr_err("Cannot read response after FPGA bitstream upload.");
return ret;
}
- if (cmd_resp != 0) {
+ if (resp != 0) {
sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
- cmd_resp);
+ resp);
return SR_ERR;
}
g_usleep(30 * 1000);
- if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot enable FPGA after bitstream upload.");
return ret;
}
{
struct dev_context *devc;
int ret;
-
- devc = sdi->priv;
-
uint16_t duty_R79, duty_R56;
uint8_t buf[2 * sizeof(uint16_t)];
uint8_t *wrptr;
+ devc = sdi->priv;
+
/* Clamp threshold setting to valid range for LA2016. */
- if (voltage > 4.0) {
- voltage = 4.0;
- } else if (voltage < -4.0) {
- voltage = -4.0;
+ if (voltage > LA2016_THR_VOLTAGE_MAX) {
+ voltage = LA2016_THR_VOLTAGE_MAX;
+ } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
+ voltage = -LA2016_THR_VOLTAGE_MAX;
}
/*
return SR_OK;
}
-static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
+/*
+ * Communicates a channel's configuration to the device after the
+ * parameters may have changed. Configuration of one channel may
+ * interfere with other channels since they share FPGA registers.
+ */
+static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
{
+ static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
+
struct dev_context *devc;
- uint8_t cfg;
+ struct pwm_setting *params;
+ uint8_t reg_base;
+ double val_f;
+ uint32_t val_u;
+ uint32_t period, duty;
+ size_t ch;
int ret;
+ uint8_t enable_all, enable_cfg, reg_val;
+ uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
+ uint8_t *wrptr;
devc = sdi->priv;
- cfg = 0;
+ if (idx >= ARRAY_SIZE(devc->pwm_setting))
+ return SR_ERR_ARG;
+ params = &devc->pwm_setting[idx];
+ if (idx >= ARRAY_SIZE(reg_bases))
+ return SR_ERR_ARG;
+ reg_base = reg_bases[idx];
- if (p1) cfg |= 1 << 0;
- if (p2) cfg |= 1 << 1;
+ /*
+ * Map application's specs to hardware register values. Do math
+ * in floating point initially, but convert to u32 eventually.
+ */
+ sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
+ idx, params->enabled ? 1 : 0, params->freq, params->duty);
+ val_f = PWM_CLOCK;
+ val_f /= params->freq;
+ val_u = val_f;
+ period = val_u;
+ val_f = period;
+ val_f *= params->duty;
+ val_f /= 100.0;
+ val_f += 0.5;
+ val_u = val_f;
+ duty = val_u;
+ sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
+ (unsigned)reg_base, (unsigned)period, (unsigned)duty);
+
+ /* Get the "enabled" state of all supported PWM channels. */
+ enable_all = 0;
+ for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
+ if (!devc->pwm_setting[ch].enabled)
+ continue;
+ enable_all |= 1U << ch;
+ }
+ enable_cfg = 1U << idx;
+ sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
+ enable_all, enable_cfg);
- sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg);
- ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg));
+ /*
+ * Disable the to-get-configured channel before its parameters
+ * will change. Or disable and exit when the channel is supposed
+ * to get turned off.
+ */
+ sr_spew("PWM config, disabling before param change.");
+ reg_val = enable_all & ~enable_cfg;
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
+ ®_val, sizeof(reg_val));
if (ret != SR_OK) {
- sr_err("Cannot setup PWM enabled state.");
+ sr_err("Cannot adjust PWM enabled state.");
return ret;
}
- devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
- devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
-
- return SR_OK;
-}
+ if (!params->enabled)
+ return SR_OK;
-static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which,
- float freq, float duty)
-{
- int CTRL_PWM[] = { REG_PWM1, REG_PWM2 };
- struct dev_context *devc;
- pwm_setting_dev_t cfg;
- pwm_setting_t *setting;
- int ret;
- uint8_t buf[2 * sizeof(uint32_t)];
- uint8_t *wrptr;
-
- devc = sdi->priv;
-
- if (which < 1 || which > ARRAY_SIZE(CTRL_PWM)) {
- sr_err("Invalid PWM channel: %d.", which);
- return SR_ERR;
- }
- if (freq > MAX_PWM_FREQ) {
- sr_err("Too high a PWM frequency: %.1f.", freq);
- return SR_ERR;
- }
- if (duty > 100 || duty < 0) {
- sr_err("Invalid PWM duty cycle: %f.", duty);
- return SR_ERR;
+ /* Write register values to device. */
+ sr_spew("PWM config, sending new parameters.");
+ wrptr = buf;
+ write_u32le_inc(&wrptr, period);
+ write_u32le_inc(&wrptr, duty);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
+ if (ret != SR_OK) {
+ sr_err("Cannot change PWM parameters.");
+ return ret;
}
- cfg.period = (uint32_t)(PWM_CLOCK / freq);
- cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
- sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty);
-
- wrptr = buf;
- write_u32le_inc(&wrptr, cfg.period);
- write_u32le_inc(&wrptr, cfg.duty);
- ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
+ /* Enable configured channel after write completion. */
+ sr_spew("PWM config, enabling after param change.");
+ reg_val = enable_all | enable_cfg;
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
+ ®_val, sizeof(reg_val));
if (ret != SR_OK) {
- sr_err("Cannot setup PWM%d configuration %d %d.",
- which, cfg.period, cfg.duty);
+ sr_err("Cannot adjust PWM enabled state.");
return ret;
}
- setting = &devc->pwm_setting[which - 1];
- setting->freq = freq;
- setting->duty = duty;
return SR_OK;
}
-static int set_defaults(const struct sr_dev_inst *sdi)
+static uint16_t get_channels_mask(const struct sr_dev_inst *sdi)
{
- struct dev_context *devc;
- int ret;
-
- devc = sdi->priv;
-
- devc->capture_ratio = LA2016_DFLT_CAPT_RATIO;
- devc->limit_samples = LA2016_DFLT_SAMPLEDEPTH;
- devc->cur_samplerate = LA2016_DFLT_SAMPLERATE;
-
- ret = set_threshold_voltage(sdi, devc->threshold_voltage);
- if (ret)
- return ret;
-
- ret = enable_pwm(sdi, 0, 0);
- if (ret)
- return ret;
-
- ret = set_pwm(sdi, 1, SR_KHZ(1), 50);
- if (ret)
- return ret;
-
- ret = set_pwm(sdi, 2, SR_KHZ(100), 50);
- if (ret)
- return ret;
-
- ret = enable_pwm(sdi, 1, 1);
- if (ret)
- return ret;
+ uint16_t channels;
+ GSList *l;
+ struct sr_channel *ch;
+
+ channels = 0;
+ for (l = sdi->channels; l; l = l->next) {
+ ch = l->data;
+ if (ch->type != SR_CHANNEL_LOGIC)
+ continue;
+ if (!ch->enabled)
+ continue;
+ channels |= 1UL << ch->index;
+ }
- return SR_OK;
+ return channels;
}
static int set_trigger_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
struct sr_trigger *trigger;
- trigger_cfg_t cfg;
+ struct trigger_cfg {
+ uint32_t channels;
+ uint32_t enabled;
+ uint32_t level;
+ uint32_t high_or_falling;
+ } cfg;
GSList *stages;
GSList *channel;
struct sr_trigger_stage *stage1;
memset(&cfg, 0, sizeof(cfg));
- cfg.channels = devc->cur_channels;
+ cfg.channels = get_channels_mask(sdi);
if (trigger && trigger->stages) {
stages = trigger->stages;
static int set_sample_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- double clock_divisor;
+ uint64_t min_samplerate, eff_samplerate;
uint16_t divider_u16;
+ uint64_t limit_samples;
uint64_t pre_trigger_samples;
uint64_t pre_trigger_memory;
uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
devc = sdi->priv;
- if (devc->cur_samplerate > devc->max_samplerate) {
+ if (devc->cur_samplerate > devc->model->samplerate) {
sr_err("Too high a sample rate: %" PRIu64 ".",
devc->cur_samplerate);
- return SR_ERR;
+ return SR_ERR_ARG;
}
-
- clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate;
- if (clock_divisor > 65535)
+ min_samplerate = devc->model->samplerate;
+ min_samplerate /= 65536;
+ if (devc->cur_samplerate < min_samplerate) {
+ sr_err("Too low a sample rate: %" PRIu64 ".",
+ devc->cur_samplerate);
return SR_ERR_ARG;
- divider_u16 = (uint16_t)(clock_divisor + 0.5);
- devc->cur_samplerate = devc->max_samplerate / divider_u16;
+ }
+ divider_u16 = devc->model->samplerate / devc->cur_samplerate;
+ eff_samplerate = devc->model->samplerate / divider_u16;
- if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
- sr_err("Too high a sample depth: %" PRIu64 ".",
- devc->limit_samples);
- return SR_ERR;
+ ret = sr_sw_limits_get_remain(&devc->sw_limits,
+ &limit_samples, NULL, NULL, NULL);
+ if (ret != SR_OK) {
+ sr_err("Cannot get acquisition limits.");
+ return ret;
+ }
+ if (limit_samples > LA2016_NUM_SAMPLES_MAX) {
+ sr_warn("Too high a sample depth: %" PRIu64 ", capping.",
+ limit_samples);
+ limit_samples = LA2016_NUM_SAMPLES_MAX;
+ }
+ if (limit_samples == 0) {
+ limit_samples = LA2016_NUM_SAMPLES_MAX;
+ sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.",
+ limit_samples);
}
/*
* limit the amount of sample memory to use for pre-trigger
* data. Only the upper 24 bits of that memory size spec get
* communicated to the device (written to its FPGA register).
+ *
+ * TODO Determine whether the pre-trigger memory size gets
+ * specified in samples or in bytes. A previous implementation
+ * suggests bytes but this is suspicious when every other spec
+ * is in terms of samples.
*/
- pre_trigger_samples = devc->limit_samples * devc->capture_ratio / 100;
- pre_trigger_memory = LA2016_PRE_MEM_LIMIT_BASE;
- pre_trigger_memory *= devc->capture_ratio;
- pre_trigger_memory /= 100;
+ if (devc->trigger_involved) {
+ pre_trigger_samples = limit_samples;
+ pre_trigger_samples *= devc->capture_ratio;
+ pre_trigger_samples /= 100;
+ pre_trigger_memory = devc->model->memory_bits;
+ pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024);
+ pre_trigger_memory /= 8; /* devc->model->channel_count ? */
+ pre_trigger_memory *= devc->capture_ratio;
+ pre_trigger_memory /= 100;
+ } else {
+ sr_dbg("No trigger setup, skipping pre-trigger config.");
+ pre_trigger_samples = 1;
+ pre_trigger_memory = 0;
+ }
+ /* Ensure non-zero value after LSB shift out in HW reg. */
+ if (pre_trigger_memory < 0x100) {
+ pre_trigger_memory = 0x100;
+ }
sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.",
- devc->cur_samplerate / 1000, devc->limit_samples);
+ eff_samplerate / SR_KHZ(1), limit_samples);
sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".",
devc->capture_ratio, pre_trigger_samples, pre_trigger_memory);
* - An 8bit register of unknown meaning. Currently always 0.
*/
wrptr = buf;
- write_u40le_inc(&wrptr, devc->limit_samples);
+ write_u40le_inc(&wrptr, limit_samples);
write_u40le_inc(&wrptr, pre_trigger_samples);
write_u24le_inc(&wrptr, pre_trigger_memory >> 8);
write_u16le_inc(&wrptr, divider_u16);
const uint8_t *rdptr;
const char *label;
- if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state))) != SR_OK) {
+ ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state));
+ if (ret != SR_OK) {
sr_err("Cannot read run state.");
return ret;
}
{
int ret;
- if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode))) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode));
+ if (ret != SR_OK) {
sr_err("Cannot configure run mode %d.", mode);
return ret;
}
devc = sdi->priv;
- if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) {
+ ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf));
+ if (ret != SR_OK) {
sr_err("Cannot read capture info.");
return ret;
}
return SR_OK;
}
-SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx,
- libusb_device *dev, uint16_t product_id)
+SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
+ struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
{
- char fw_file[1024];
- snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
- return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
+ struct dev_context *devc;
+ char *fw_file;
+ int ret;
+
+ devc = sdi ? sdi->priv : NULL;
+
+ fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id);
+ sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file);
+
+ ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
+ if (ret != SR_OK) {
+ g_free(fw_file);
+ return ret;
+ }
+
+ if (devc) {
+ devc->mcu_firmware = fw_file;
+ fw_file = NULL;
+ }
+ g_free(fw_file);
+
+ return SR_OK;
}
SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
return ret;
cmd = 0;
- if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
+ if (ret != SR_OK) {
sr_err("Cannot send command to stop sampling.");
return ret;
}
devc = sdi->priv;
usb = sdi->conn;
- if ((ret = get_capture_info(sdi)) != SR_OK)
+ ret = get_capture_info(sdi);
+ if (ret != SR_OK)
return ret;
devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".",
devc->n_transfer_packets_to_read, devc->read_pos);
- if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot reset USB bulk state.");
return ret;
}
wrptr = wrbuf;
write_u32le_inc(&wrptr, devc->read_pos);
write_u32le_inc(&wrptr, devc->n_bytes_to_read);
- if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf);
+ if (ret != SR_OK) {
sr_err("Cannot send USB bulk config.");
return ret;
}
- if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot unblock USB bulk transfers.");
return ret;
}
devc->transfer = libusb_alloc_transfer(0);
libusb_fill_bulk_transfer(devc->transfer,
usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
- buffer, to_read,
- cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
+ buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
- if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
+ ret = libusb_submit_transfer(devc->transfer);
+ if (ret != 0) {
sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret));
libusb_free_transfer(devc->transfer);
devc->transfer = NULL;
return SR_OK;
}
+/*
+ * A chunk (received via USB) contains a number of transfers (USB length
+ * divided by 16) which contain a number of packets (5 per transfer) which
+ * contain a number of samples (8bit repeat count per 16bit sample data).
+ */
static void send_chunk(struct sr_dev_inst *sdi,
- const uint8_t *packets, unsigned int num_tfers)
+ const uint8_t *packets, size_t num_xfers)
{
struct dev_context *devc;
- struct sr_datafeed_logic logic;
- struct sr_datafeed_packet sr_packet;
- unsigned int max_samples, n_samples, total_samples, free_n_samples;
- unsigned int i, j, k;
- gboolean do_signal_trigger;
- uint8_t *wp;
+ size_t num_pkts;
const uint8_t *rp;
- uint16_t state;
- uint8_t repetitions;
- uint8_t sample_buff[sizeof(state)];
+ uint16_t sample_value;
+ size_t repetitions;
+ uint8_t sample_buff[sizeof(sample_value)];
devc = sdi->priv;
- logic.unitsize = sizeof(sample_buff);
- logic.data = devc->convbuffer;
-
- sr_packet.type = SR_DF_LOGIC;
- sr_packet.payload = &logic;
-
- max_samples = devc->convbuffer_size / sizeof(sample_buff);
- n_samples = 0;
- wp = devc->convbuffer;
- total_samples = 0;
- do_signal_trigger = FALSE;
+ /* Ignore incoming USB data after complete sample data download. */
+ if (devc->download_finished)
+ return;
if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) {
- std_session_send_df_trigger(sdi);
+ feed_queue_logic_send_trigger(devc->feed_queue);
devc->trigger_marked = TRUE;
}
rp = packets;
- for (i = 0; i < num_tfers; i++) {
- for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) {
- free_n_samples = max_samples - n_samples;
- if (free_n_samples < 256 || do_signal_trigger) {
- logic.length = n_samples * 2;
- sr_session_send(sdi, &sr_packet);
- n_samples = 0;
- wp = devc->convbuffer;
- if (do_signal_trigger) {
- std_session_send_df_trigger(sdi);
- do_signal_trigger = FALSE;
- }
- }
+ while (num_xfers--) {
+ num_pkts = NUM_PACKETS_IN_CHUNK;
+ while (num_pkts--) {
- state = read_u16le_inc(&rp);
+ sample_value = read_u16le_inc(&rp);
repetitions = read_u8_inc(&rp);
- write_u16le((void *)&sample_buff, state);
- for (j = 0; j < repetitions; j++) {
- memcpy(wp, sample_buff, logic.unitsize);
- wp += logic.unitsize;
- }
- n_samples += repetitions;
- total_samples += repetitions;
devc->total_samples += repetitions;
+
+ write_u16le(sample_buff, sample_value);
+ feed_queue_logic_submit(devc->feed_queue,
+ sample_buff, repetitions);
+ sr_sw_limits_update_samples_read(&devc->sw_limits,
+ repetitions);
+
if (devc->trigger_involved && !devc->trigger_marked) {
if (!--devc->n_reps_until_trigger) {
+ feed_queue_logic_send_trigger(devc->feed_queue);
devc->trigger_marked = TRUE;
- do_signal_trigger = TRUE;
sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
devc->total_samples,
(double)devc->total_samples / devc->cur_samplerate * 1e3);
}
(void)read_u8_inc(&rp); /* Skip sequence number. */
}
- if (n_samples) {
- logic.length = n_samples * logic.unitsize;
- sr_session_send(sdi, &sr_packet);
- if (do_signal_trigger) {
- std_session_send_df_trigger(sdi);
- }
+
+ if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) {
+ sr_dbg("Acquisition limit reached.");
+ devc->download_finished = TRUE;
}
- sr_dbg("Send_chunk done after %u samples.", total_samples);
+ if (devc->download_finished) {
+ sr_dbg("Download finished, flushing session feed queue.");
+ feed_queue_logic_flush(devc->feed_queue);
+ }
+ sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
}
static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
struct sr_dev_inst *sdi;
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
+ size_t num_xfers;
int ret;
sdi = transfer->user_data;
sr_dbg("receive_transfer(): status %s received %d bytes.",
libusb_error_name(transfer->status), transfer->actual_length);
-
- if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) {
- sr_err("USB bulk transfer timeout.");
- devc->download_finished = TRUE;
- }
- send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH);
+ /*
+ * Implementation detail: A USB transfer timeout is not fatal
+ * here. We just process whatever was received, empty input is
+ * perfectly acceptable. Reaching (or exceeding) the sw limits
+ * or exhausting the device's captured data will complete the
+ * sample data download.
+ */
+ num_xfers = transfer->actual_length / TRANSFER_PACKET_LENGTH;
+ send_chunk(sdi, transfer->buffer, num_xfers);
devc->n_bytes_to_read -= transfer->actual_length;
if (devc->n_bytes_to_read) {
transfer->buffer, to_read,
receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS);
- if ((ret = libusb_submit_transfer(transfer)) == 0)
+ ret = libusb_submit_transfer(transfer);
+ if (ret == 0)
return;
sr_err("Cannot submit another USB transfer: %s.",
libusb_error_name(ret));
struct dev_context *devc;
struct drv_context *drvc;
struct timeval tv;
+ int ret;
(void)fd;
(void)revents;
devc = sdi->priv;
drvc = sdi->driver->context;
+ /*
+ * Wait for the acquisition to complete in hardware.
+ * Periodically check a potentially configured msecs timeout.
+ */
if (!devc->completion_seen) {
if (!la2016_is_idle(sdi)) {
+ if (sr_sw_limits_check(&devc->sw_limits)) {
+ devc->sw_limits.limit_msec = 0;
+ sr_dbg("Limit reached. Stopping acquisition.");
+ la2016_stop_acquisition(sdi);
+ }
/* Not yet ready for sample data download. */
return TRUE;
}
+ sr_dbg("Acquisition completion seen (hardware).");
+ devc->sw_limits.limit_msec = 0;
devc->completion_seen = TRUE;
devc->download_finished = FALSE;
devc->trigger_marked = FALSE;
devc->total_samples = 0;
- /* We can start downloading sample data. */
- if (la2016_start_download(sdi, receive_transfer) != SR_OK) {
+
+ /* Initiate the download of acquired sample data. */
+ std_session_send_df_frame_begin(sdi);
+ ret = la2016_start_download(sdi, receive_transfer);
+ if (ret != SR_OK) {
sr_err("Cannot start acquisition data download.");
return FALSE;
}
sr_dbg("Acquisition data download started.");
- std_session_send_df_frame_begin(sdi);
return TRUE;
}
+ /* Handle USB reception. Drives sample data download. */
tv.tv_sec = tv.tv_usec = 0;
libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
+ /* Postprocess completion of sample data download. */
if (devc->download_finished) {
sr_dbg("Download finished, post processing.");
- std_session_send_df_frame_end(sdi);
-
- usb_source_remove(sdi->session, drvc->sr_ctx);
- std_session_send_df_end(sdi);
la2016_stop_acquisition(sdi);
-
- g_free(devc->convbuffer);
- devc->convbuffer = NULL;
-
+ usb_source_remove(sdi->session, drvc->sr_ctx);
devc->transfer = NULL;
+ feed_queue_logic_flush(devc->feed_queue);
+ feed_queue_logic_free(devc->feed_queue);
+ devc->feed_queue = NULL;
+ std_session_send_df_frame_end(sdi);
+ std_session_send_df_end(sdi);
+
sr_dbg("Download finished, done post processing.");
}
return TRUE;
}
-SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
+SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
+ gboolean show_message)
{
struct dev_context *devc;
- uint16_t state;
uint8_t buf[8];
+ size_t rdoff, rdlen;
const uint8_t *rdptr;
uint8_t date_yy, date_mm;
uint8_t dinv_yy, dinv_mm;
uint8_t magic;
- const char *bitstream_fn;
+ size_t model_idx;
+ const struct kingst_model *model;
int ret;
devc = sdi->priv;
* to 2020-04. This information can help identify the vintage of
* devices when unknown magic numbers are seen.
*/
- ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, buf, 4 * sizeof(uint8_t));
- if (ret != SR_OK) {
+ rdoff = 0x20;
+ rdlen = 4 * sizeof(uint8_t);
+ ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen);
+ if (ret != SR_OK && !show_message) {
+ /* Non-fatal weak attempt during probe. Not worth logging. */
+ sr_dbg("Cannot access EEPROM.");
+ return SR_ERR_IO;
+ } else if (ret != SR_OK) {
+ /* Failed attempt in regular use. Non-fatal. Worth logging. */
sr_err("Cannot read manufacture date in EEPROM.");
} else {
+ if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
+ GString *txt;
+ txt = sr_hexdump_new(buf, rdlen);
+ sr_spew("Manufacture date bytes %s.", txt->str);
+ sr_hexdump_free(txt);
+ }
rdptr = &buf[0];
date_yy = read_u8_inc(&rdptr);
date_mm = read_u8_inc(&rdptr);
* do not match the hardware model. An LA1016 won't become a
* LA2016 by faking its EEPROM content.
*/
- if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) {
+ devc->identify_magic = 0;
+ rdoff = 0x08;
+ rdlen = 8 * sizeof(uint8_t);
+ ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen);
+ if (ret != SR_OK) {
sr_err("Cannot read EEPROM device identifier bytes.");
return ret;
}
+ if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
+ GString *txt;
+ txt = sr_hexdump_new(buf, rdlen);
+ sr_spew("EEPROM magic bytes %s.", txt->str);
+ sr_hexdump_free(txt);
+ }
if ((buf[0] ^ buf[1]) == 0xff) {
/* Primary copy of magic passes complement check. */
- sr_dbg("Using primary copy of device type magic number.");
magic = buf[0];
+ sr_dbg("Using primary magic, value %d.", (int)magic);
} else if ((buf[4] ^ buf[5]) == 0xff) {
/* Backup copy of magic passes complement check. */
- sr_dbg("Using backup copy of device type magic number.");
magic = buf[4];
+ sr_dbg("Using backup magic, value %d.", (int)magic);
} else {
sr_err("Cannot find consistent device type identification.");
magic = 0;
}
- sr_dbg("Device type: magic number is %hhu.", magic);
-
- /* Select the FPGA bitstream depending on the model. */
- switch (magic) {
- case 2:
- bitstream_fn = FPGA_FW_LA2016;
- devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
- break;
- case 3:
- bitstream_fn = FPGA_FW_LA1016;
- devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
- break;
- case 8:
- bitstream_fn = FPGA_FW_LA2016A;
- devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
- break;
- case 9:
- bitstream_fn = FPGA_FW_LA1016A;
- devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
- break;
- default:
- bitstream_fn = NULL;
+ devc->identify_magic = magic;
+
+ devc->model = NULL;
+ for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
+ model = &models[model_idx];
+ if (model->magic != magic)
+ continue;
+ devc->model = model;
+ sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
+ model->name, model->channel_count,
+ model->samplerate / SR_MHZ(1));
+ devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
+ model->fpga_stem);
+ sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
break;
}
- if (!bitstream_fn || !*bitstream_fn) {
+ if (!devc->model) {
sr_err("Cannot identify as one of the supported models.");
return SR_ERR;
}
- if (check_fpga_bitstream(sdi) != SR_OK) {
+ return SR_OK;
+}
+
+SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ const char *bitstream_fn;
+ int ret;
+ uint16_t state;
+
+ devc = sdi->priv;
+ bitstream_fn = devc ? devc->fpga_bitstream : "";
+
+ ret = check_fpga_bitstream(sdi);
+ if (ret != SR_OK) {
ret = upload_fpga_bitstream(sdi, bitstream_fn);
if (ret != SR_OK) {
sr_err("Cannot upload FPGA bitstream.");
sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state);
}
- if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot reset USB bulk transfer.");
return ret;
}
sr_dbg("Device should be initialized.");
- ret = set_defaults(sdi);
- if (ret != SR_OK)
- return ret;
-
return SR_OK;
}
-SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
+SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
{
int ret;
- if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
+ ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
+ if (ret != SR_OK) {
sr_err("Cannot deinitialize device's FPGA.");
return ret;
}
return SR_OK;
}
+
+SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
+{
+ return set_pwm_config(sdi, idx);
+}
projects / libsigrok.git / blobdiff