#define MAX_PWM_FREQ SR_MHZ(20)
#define PWM_CLOCK SR_MHZ(200)
-/* registers for control request 32: */
-#define CTRL_RUN 0x00
-#define CTRL_PWM_EN 0x02
-#define CTRL_BULK 0x10 /* can be read to get 12 byte sampling_info (III) */
-#define CTRL_SAMPLING 0x20
-#define CTRL_TRIGGER 0x30
-#define CTRL_THRESHOLD 0x48
-#define CTRL_PWM1 0x70
-#define CTRL_PWM2 0x78
+/* usb vendor class control requests to the cypress FX2 microcontroller */
+#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
+#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_ENABLE 0x10
+#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
+#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
+#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
+
+/*
+ * fpga spi register addresses for control request CMD_FPGA_SPI:
+ * There are around 60 byte-wide registers within the fpga and
+ * these are the base addresses used for accessing them.
+ * On the spi bus, the msb of the address byte is set for read
+ * and cleared for write, but that is handled by the fx2 mcu
+ * as appropriate. In this driver code just use IN transactions
+ * to read, OUT to write.
+ */
+#define REG_RUN 0x00 /* read capture status, write capture start */
+#define REG_PWM_EN 0x02 /* user pwm channels on/off */
+#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
+#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */
+#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */
+#define REG_TRIGGER 0x20 /* write level and edge trigger config */
+#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */
+#define REG_PWM1 0x70 /* write config for user pwm1 */
+#define REG_PWM2 0x78 /* write config for user pwm2 */
static int ctrl_in(const struct sr_dev_inst *sdi,
uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
devc->bitstream_size = (uint32_t)bitstream.size;
wrptr = buffer;
write_u32le_inc(&wrptr, devc->bitstream_size);
- if ((ret = ctrl_out(sdi, 80, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
sr_err("failed to give upload init command");
sr_resource_close(drvc->sr_ctx, &bitstream);
return ret;
return ret;
sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
- if ((ret = ctrl_in(sdi, 80, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
sr_err("failed to read response after FPGA bitstream upload");
return ret;
}
g_usleep(30000);
- if ((ret = ctrl_out(sdi, 16, 0x01, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
sr_err("failed enable fpga");
return ret;
}
static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
{
struct dev_context *devc;
- float o1, o2, v1, v2, f;
- uint32_t cfgval;
- uint8_t buffer[sizeof(uint32_t)];
- uint8_t *wrptr;
int ret;
devc = sdi->priv;
- o1 = 15859969; v1 = 0.45;
- o2 = 15860333; v2 = 1.65;
- f = (o2 - o1) / (v2 - v1);
- cfgval = (uint32_t)(o1 + (voltage - v1) * f);
- sr_dbg("set threshold voltage %.2fV, raw value 0x%lx",
- voltage, (unsigned long)cfgval);
- wrptr = buffer;
- write_u32le_inc(&wrptr, cfgval);
- ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, buffer, wrptr - buffer);
+ uint16_t duty_R79,duty_R56;
+ uint8_t buf[2 * sizeof(uint16_t)];
+ uint8_t *wrptr;
+
+ /* clamp threshold setting within valid range for LA2016 */
+ if (voltage > 4.0) {
+ voltage = 4.0;
+ }
+ else if (voltage < -4.0) {
+ voltage = -4.0;
+ }
+
+ /*
+ * The fpga has two programmable pwm outputs which feed a dac that
+ * is used to adjust input offset. The dac changes the input
+ * swing around the fixed fpga input threshold.
+ * The two pwm outputs can be seen on R79 and R56 respectvely.
+ * Frequency is fixed at 100kHz and duty is varied.
+ * The R79 pwm uses just three settings.
+ * The R56 pwm varies with required threshold and its behaviour
+ * also changes depending on the setting of R79 PWM.
+ */
+
+ /*
+ * calculate required pwm duty register values from requested threshold voltage
+ * see last page of schematic (on wiki) for an explanation of these numbers
+ */
+ if (voltage >= 2.9) {
+ duty_R79 = 0; /* this pwm is off (0V)*/
+ duty_R56 = (uint16_t)(302 * voltage - 363);
+ }
+ else if (voltage <= -0.4) {
+ duty_R79 = 0x02D7; /* 72% duty */
+ duty_R56 = (uint16_t)(302 * voltage + 1090);
+ }
+ else {
+ duty_R79 = 0x00f2; /* 25% duty */
+ duty_R56 = (uint16_t)(302 * voltage + 121);
+ }
+
+ /* clamp duty register values at sensible limits */
+ if (duty_R56 < 10) {
+ duty_R56 = 10;
+ }
+ else if (duty_R56 > 1100) {
+ duty_R56 = 1100;
+ }
+
+ sr_dbg("set threshold voltage %.2fV", voltage);
+ sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79);
+
+ wrptr = buf;
+ write_u16le_inc(&wrptr, duty_R56);
+ write_u16le_inc(&wrptr, duty_R79);
+
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
if (ret != SR_OK) {
- sr_err("Error setting %.2fV threshold voltage (%d)",
- voltage, ret);
+ sr_err("error setting new threshold voltage of %.2fV", voltage);
return ret;
}
devc->threshold_voltage = voltage;
if (p2) cfg |= 1 << 1;
sr_dbg("set pwm enable %d %d", p1, p2);
- ret = ctrl_out(sdi, 32, CTRL_PWM_EN, 0, &cfg, sizeof(cfg));
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg));
if (ret != SR_OK) {
sr_err("error setting new pwm enable 0x%02x", cfg);
return ret;
static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
{
- int CTRL_PWM[] = { CTRL_PWM1, CTRL_PWM2 };
+ int CTRL_PWM[] = { REG_PWM1, REG_PWM2 };
struct dev_context *devc;
pwm_setting_dev_t cfg;
pwm_setting_t *setting;
wrptr = buf;
write_u32le_inc(&wrptr, cfg.period);
write_u32le_inc(&wrptr, cfg.duty);
- ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
return ret;
write_u32le_inc(&wrptr, cfg.enabled);
write_u32le_inc(&wrptr, cfg.level);
write_u32le_inc(&wrptr, cfg.high_or_falling);
- ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, buf, wrptr - buf);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting trigger config!");
return ret;
{
struct dev_context *devc;
double clock_divisor;
- uint64_t psa;
uint64_t total;
int ret;
uint16_t divisor;
sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
- psa = devc->pre_trigger_size * 256;
wrptr = buf;
write_u32le_inc(&wrptr, devc->limit_samples);
- write_u48le_inc(&wrptr, psa);
- write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
- write_u16le_inc(&wrptr, clock_divisor);
+ write_u8_inc(&wrptr, 0);
+ write_u32le_inc(&wrptr, devc->pre_trigger_size);
+ write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00 );
+ write_u16le_inc(&wrptr, divisor);
+ write_u8_inc(&wrptr, 0);
- ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, buf, wrptr - buf);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting sample config!");
return ret;
uint16_t state;
int ret;
- if ((ret = ctrl_in(sdi, 32, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) {
sr_err("failed to read run state!");
return ret;
}
{
int ret;
- if ((ret = ctrl_out(sdi, 32, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
sr_err("failed to send set-run-mode command %d", fast_blinking);
return ret;
}
devc = sdi->priv;
- if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, buf, sizeof(buf))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) {
sr_err("failed to read capture info!");
return ret;
}
return ret;
cmd = 0;
- if ((ret = ctrl_out(sdi, 32, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) {
sr_err("failed to send stop sampling command");
return ret;
}
sr_dbg("want to read %d tfer-packets starting from pos %d",
devc->n_transfer_packets_to_read, devc->read_pos);
- if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to reset bulk state");
return ret;
}
wrptr = wrbuf;
write_u32le_inc(&wrptr, devc->read_pos);
write_u32le_inc(&wrptr, devc->n_bytes_to_read);
- if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
sr_err("failed to send bulk config");
return ret;
}
- if ((ret = ctrl_out(sdi, 48, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to unblock bulk transfers");
return ret;
}
devc = sdi->priv;
- if ((ret = ctrl_in(sdi, 162, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
sr_err("failed to read i1");
return ret;
}
sr_dbg("i1: 0x%08x", i1);
- if ((ret = ctrl_in(sdi, 162, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
sr_err("failed to read i2");
return ret;
}
unknown_cmd1 = unknown_cmd1_342;
expected_unknown_resp1 = expected_unknown_resp1_342;
}
- if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
sr_err("failed to send unknown_cmd1");
return ret;
}
g_usleep(80 * 1000);
- if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
sr_err("failed to read unknown_resp1");
return ret;
}
if (state != 0x85e9)
sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
- if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
sr_err("failed to send unknown_cmd2");
return ret;
}
g_usleep(80 * 1000);
- if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
sr_err("failed to read unknown_resp2");
return ret;
}
if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
sr_dbg("unknown_cmd2 response is not as expected!");
- if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to send unknown_cmd3");
return ret;
}
{
int ret;
- if ((ret = ctrl_out(sdi, 16, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to send deinit command");
return ret;
}
projects / libsigrok.git / blobdiff