#define MAX_SAMPLE_DELAY (6 * 256)
#define DEV_CAPS_16BIT_POS 0
+#define DEV_CAPS_AX_ANALOG_POS 1
#define DEV_CAPS_16BIT (1 << DEV_CAPS_16BIT_POS)
+#define DEV_CAPS_AX_ANALOG (1 << DEV_CAPS_AX_ANALOG_POS)
#define DSLOGIC_FPGA_FIRMWARE "dreamsourcelab-dslogic-fpga.fw"
#define DSCOPE_FPGA_FIRMWARE "dreamsourcelab-dscope-fpga.fw"