};
static const uint32_t dslogic_devopts[] = {
- SR_CONF_CONTINUOUS | SR_CONF_SET,
+ SR_CONF_CONTINUOUS | SR_CONF_SET | SR_CONF_GET,
SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_CONN | SR_CONF_GET,
SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
static const int32_t soft_trigger_matches[] = {
SR_TRIGGER_EDGE,
};
+/* Names assigned to available edge slope choices. */
+static const char *const signal_edge_names[] = {
+ [DS_EDGE_RISING] = "rising",
+ [DS_EDGE_FALLING] = "falling",
+};
+
static const struct {
int range;
gdouble low;
gdouble high;
} volt_thresholds[] = {
- { DS_VOLTAGE_RANGE_18_33_V, 0.7, 1.4 },
- { DS_VOLTAGE_RANGE_5_V, 1.4, 3.6 },
+ { DS_VOLTAGE_RANGE_18_33_V, 0.7, 1.4 },
+ { DS_VOLTAGE_RANGE_5_V, 1.4, 3.6 },
};
static const uint64_t samplerates[] = {
struct sr_usb_dev_inst *usb;
usb = sdi->conn;
+
if (!usb->devhdl)
return SR_ERR;
return SR_OK;
}
-static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
- const struct sr_channel_group *cg)
+static int config_get(uint32_t key, GVariant **data,
+ const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
case SR_CONF_CAPTURE_RATIO:
*data = g_variant_new_uint64(devc->capture_ratio);
break;
+ case SR_CONF_EXTERNAL_CLOCK:
+ *data = g_variant_new_boolean(devc->dslogic_external_clock);
+ break;
+ case SR_CONF_CONTINUOUS:
+ *data = g_variant_new_boolean(devc->dslogic_continuous_mode);
+ break;
+ case SR_CONF_CLOCK_EDGE:
+ i = devc->dslogic_clock_edge;
+ if (i >= ARRAY_SIZE(signal_edge_names))
+ return SR_ERR_BUG;
+ *data = g_variant_new_string(signal_edge_names[0]);
+ break;
default:
return SR_ERR_NA;
}
return SR_OK;
}
-static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
- const struct sr_channel_group *cg)
+/*
+ * Helper for mapping a string-typed configuration value to an index
+ * within a table of possible values.
+ */
+static int lookup_index(GVariant *value, const char *const *table, int len)
+{
+ const char *entry;
+ int i;
+
+ entry = g_variant_get_string(value, NULL);
+ if (!entry)
+ return -1;
+
+ /* Linear search is fine for very small tables. */
+ for (i = 0; i < len; i++) {
+ if (strcmp(entry, table[i]) == 0)
+ return i;
+ }
+
+ return -1;
+}
+
+static int config_set(uint32_t key, GVariant *data,
+ const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
uint64_t arg;
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V);
else
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
- }else if (!strcmp(devc->profile->model, "DSLogic Pro")){
+ } else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
}
break;
+ case SR_CONF_EXTERNAL_CLOCK:
+ devc->dslogic_external_clock = g_variant_get_boolean(data);
+ break;
+ case SR_CONF_CONTINUOUS:
+ devc->dslogic_continuous_mode = g_variant_get_boolean(data);
+ break;
+ case SR_CONF_CLOCK_EDGE:
+ i = lookup_index(data, signal_edge_names,
+ ARRAY_SIZE(signal_edge_names));
+ if (i < 0)
+ return SR_ERR_ARG;
+ devc->dslogic_clock_edge = i;
+ break;
default:
ret = SR_ERR_NA;
}
return ret;
}
-static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
- const struct sr_channel_group *cg)
+static int config_list(uint32_t key, GVariant **data,
+ const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
GVariant *gvar, *range[2];
scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
break;
case SR_CONF_DEVICE_OPTIONS:
- if (!sdi)
+ if (!sdi) {
*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
- drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
- else{
+ drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
+ } else {
devc = sdi->priv;
if (!devc->dslogic)
*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
}
break;
case SR_CONF_VOLTAGE_THRESHOLD:
- if (!sdi->priv) return SR_ERR_ARG;
+ if (!sdi->priv)
+ return SR_ERR_ARG;
devc = sdi->priv;
- if (!devc->dslogic) return SR_ERR_NA;
+ if (!devc->dslogic)
+ return SR_ERR_NA;
g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) {
range[0] = g_variant_new_double(volt_thresholds[i].low);
*data = g_variant_builder_end(&gvb);
break;
case SR_CONF_SAMPLERATE:
- if (!sdi->priv)
- return SR_ERR_ARG;
devc = sdi->priv;
g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), devc->samplerates,
soft_trigger_matches, ARRAY_SIZE(soft_trigger_matches),
sizeof(int32_t));
break;
+ case SR_CONF_CLOCK_EDGE:
+ *data = g_variant_new_strv(signal_edge_names,
+ ARRAY_SIZE(signal_edge_names));
+ break;
default:
return SR_ERR_NA;
}
devc->trigger_fired = TRUE;
num_transfers = fx2lafw_get_number_of_transfers(devc);
+
+ //if (devc->dslogic)
+ // num_transfers = dslogic_get_number_of_transfers(devc);
+
+ if (devc->dslogic) {
+ if (devc->cur_samplerate == SR_MHZ(100))
+ num_transfers = 16;
+ else if (devc->cur_samplerate == SR_MHZ(200))
+ num_transfers = 8;
+ else if (devc->cur_samplerate == SR_MHZ(400))
+ num_transfers = 4;
+ }
+
size = fx2lafw_get_buffer_size(devc);
devc->submitted_transfers = 0;
libusb_fill_bulk_transfer(transfer, usb->devhdl,
endpoint | LIBUSB_ENDPOINT_IN, buf, size,
fx2lafw_receive_transfer, (void *)sdi, timeout);
+ sr_info("submitting transfer: %d", i);
if ((ret = libusb_submit_transfer(transfer)) != 0) {
sr_err("Failed to submit transfer: %s.",
libusb_error_name(ret));
} else if (transfer->status == LIBUSB_TRANSFER_COMPLETED
&& transfer->actual_length == sizeof(struct dslogic_trigger_pos)) {
tpos = (struct dslogic_trigger_pos *)transfer->buffer;
- sr_info("tpos real_pos %d ram_saddr %d cnt %d", tpos->real_pos, tpos->ram_saddr, tpos->remain_cnt);
- devc->trigger_pos = tpos->real_pos;
+ sr_info("tpos real_pos %d ram_saddr %d cnt %d", tpos->real_pos,
+ tpos->ram_saddr, tpos->remain_cnt);
+ devc->trigger_pos = tpos->real_pos;
g_free(tpos);
start_transfers(sdi);
}
if ((ret = dslogic_fpga_configure(sdi)) != SR_OK)
return ret;
- /* if this is a dslogic pro, set the voltage threshold */
+ /* If this is a DSLogic Pro, set the voltage threshold. */
if (!strcmp(devc->profile->model, "DSLogic Pro")){
- if(devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_18_33_V){
+ if (devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_18_33_V) {
dslogic_set_vth(sdi, 1.4);
- }else{
+ } else {
dslogic_set_vth(sdi, 3.3);
}
}
projects / libsigrok.git / blobdiff