#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
+#define DS_MAX_TRIG_PERCENT 90
#define DS_MODE_TRIG_EN (1 << 0)
#define DS_MODE_CLK_TYPE (1 << 1)
#define DS_MODE_EXT_TEST (1 << 14)
#define DS_MODE_INT_TEST (1 << 15)
+#define DSLOGIC_ATOMIC_SAMPLES (1 << 6)
+
enum dslogic_operation_modes {
DS_OP_NORMAL,
DS_OP_INTERNAL_TEST,
DS_OP_LOOPBACK_TEST,
};
-enum {
- DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
- DS_VOLTAGE_RANGE_5_V, /* 5V logic */
-};
-
enum {
DS_EDGE_RISING,
DS_EDGE_FALLING,
SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
-SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
#endif