* are available to applications and plugin features. Can libsigrok's
* asix-sigma driver store configuration data there, to avoid expensive
* operations (think: firmware re-load).
+ *
+ * Update: The documentation may be incorrect, or the FPGA netlist may
+ * be incomplete. Experiments show that registers beyond 0x0f can get
+ * accessed, USB communication passes, but data bytes are always 0xff.
+ * Are several firmware versions around, and the documentation does not
+ * match the one that ships with sigrok?
*/
enum sigma_write_register {
WRITE_PIN_VIEW = 7,
/* Unassigned register locations. */
WRITE_TEST = 15,
+ /* Reserved for plugin features. */
+ REG_PLUGIN_START = 16,
+ REG_PLUGIN_STOP = 256,
};
enum sigma_read_register {
READ_PIN_VIEW = 13,
/* Unassigned register location. */
READ_TEST = 15,
+ /* Reserved for plugin features. See above. */
};
#define HI4(b) (((b) >> 4) & 0x0f)
#define BIT_MASK(l) ((1UL << (l)) - 1)
-#define TRGSEL_SELC_MASK BIT_MASK(2)
-#define TRGSEL_SELC_SHIFT 0
-#define TRGSEL_SELPRESC_MASK BIT_MASK(4)
-#define TRGSEL_SELPRESC_SHIFT 4
+#define CLKSEL_CLKSEL8 (1 << 0)
+#define CLKSEL_PINMASK BIT_MASK(4)
+#define CLKSEL_RISING (1 << 4)
+#define CLKSEL_FALLING (1 << 5)
+
#define TRGSEL_SELINC_MASK BIT_MASK(2)
#define TRGSEL_SELINC_SHIFT 0
#define TRGSEL_SELRES_MASK BIT_MASK(2)
#define TRGSEL_SELA_SHIFT 4
#define TRGSEL_SELB_MASK BIT_MASK(2)
#define TRGSEL_SELB_SHIFT 6
+#define TRGSEL_SELC_MASK BIT_MASK(2)
+#define TRGSEL_SELC_SHIFT 8
+#define TRGSEL_SELPRESC_MASK BIT_MASK(4)
+#define TRGSEL_SELPRESC_SHIFT 12
+
+enum trgsel_selcode_t {
+ TRGSEL_SELCODE_LEVEL = 0,
+ TRGSEL_SELCODE_FALL = 1,
+ TRGSEL_SELCODE_RISE = 2,
+ TRGSEL_SELCODE_EVENT = 3,
+ TRGSEL_SELCODE_NEVER = 3,
+};
-#define TRGSEL2_PINS_MASK (0x07 << 0)
+#define TRGSEL2_PINS_MASK BIT_MASK(3)
#define TRGSEL2_PINPOL_RISE (1 << 3)
-#define TRGSEL2_LUT_ADDR_MASK (0x0f << 0)
+#define TRGSEL2_LUT_ADDR_MASK BIT_MASK(4)
#define TRGSEL2_LUT_WRITE (1 << 4)
#define TRGSEL2_RESET (1 << 5)
#define TRGSEL2_LEDSEL0 (1 << 6)
/* The effect of all these are still a bit unclear. */
struct triggerinout {
- uint8_t trgout_resistor_enable : 1;
- uint8_t trgout_resistor_pullup : 1;
- uint8_t reserved1 : 1;
- uint8_t trgout_bytrigger : 1;
- uint8_t trgout_byevent : 1;
- uint8_t trgout_bytriggerin : 1;
- uint8_t reserved2 : 2;
-
- /* Should be set same as the first two */
- uint8_t trgout_resistor_enable2 : 1;
- uint8_t trgout_resistor_pullup2 : 1;
-
- uint8_t reserved3 : 1;
- uint8_t trgout_long : 1;
- uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
- uint8_t trgin_negate : 1;
- uint8_t trgout_enable : 1;
- uint8_t trgin_enable : 1;
+ gboolean trgout_resistor_enable, trgout_resistor_pullup;
+ gboolean trgout_resistor_enable2, trgout_resistor_pullup2;
+ gboolean trgout_bytrigger, trgout_byevent, trgout_bytriggerin;
+ gboolean trgout_long, trgout_pin; /* 1ms pulse, 1k resistor */
+ gboolean trgin_negate, trgout_enable, trgin_enable;
};
struct triggerlut {
- /* The actual LUTs. */
uint16_t m0d[4], m1d[4], m2d[4];
- uint16_t m3, m3s, m4;
-
- /* Parameters should be sent as a single register write. */
+ uint16_t m3q, m3s, m4;
struct {
- uint8_t selc : 2;
- uint8_t selpresc : 6;
-
- uint8_t selinc : 2;
- uint8_t selres : 2;
- uint8_t sela : 2;
- uint8_t selb : 2;
-
- uint16_t cmpb;
- uint16_t cmpa;
+ uint8_t selpresc;
+ uint8_t sela, selb, selc;
+ uint8_t selinc, selres;
+ uint16_t cmpa, cmpb;
} params;
};
SIGMA_FW_FREQ,
};
+enum ext_clock_edge_t {
+ SIGMA_CLOCK_EDGE_RISING,
+ SIGMA_CLOCK_EDGE_FALLING,
+ SIGMA_CLOCK_EDGE_EITHER,
+};
+
struct submit_buffer;
struct dev_context {
struct ftdi_context ctx;
gboolean is_open, must_close;
} ftdi;
- uint64_t samplerate;
+ struct {
+ uint64_t samplerate;
+ gboolean use_ext_clock;
+ size_t clock_pin;
+ enum ext_clock_edge_t clock_edge;
+ } clock;
struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */
struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */
struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */
enum sigma_firmware_idx firmware_idx;
- int num_channels;
- int samples_per_event;
+ size_t num_channels;
+ size_t samples_per_event;
uint64_t capture_ratio;
struct sigma_trigger trigger;
- int use_triggers;
+ gboolean use_triggers;
struct sigma_state state;
struct submit_buffer *buffer;
};
SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_force_close(struct dev_context *devc);
+/* Save configuration across sessions, to reduce cost of continuation. */
+SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi);
+SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi);
+
/* Send register content (simple and complex) to the hardware. */
SR_PRIV int sigma_write_register(struct dev_context *devc,
uint8_t reg, uint8_t *data, size_t len);
/* Samplerate constraints check, get/set/list helpers. */
SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate);
-SR_PRIV uint64_t sigma_get_samplerate(const struct sr_dev_inst *sdi);
SR_PRIV GVariant *sigma_get_samplerates_list(void);
/* Preparation of data acquisition, spec conversion, hardware configuration. */
projects / libsigrok.git / blobdiff